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Fix zero padding when printing registers

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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
This commit is contained in:
Erik Bjorge
2019-11-01 13:53:36 -07:00
committed by BrentHoltsclaw
parent ca2c92792d
commit 6b8d94c854
1 changed files with 1 additions and 1 deletions
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chipsec/chipset.py
+1 -1
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@@ -1014,7 +1014,7 @@ class Chipset:
reg = self.get_register_def( reg_name, bus_index )
rtype = reg['type']
reg_str = ''
reg_val_str = "0x{:{width}X}".format(reg_val,width=(int(reg['size'],16)*2))
reg_val_str = "0x{:0{width}X}".format(reg_val,width=(int(reg['size'],16)*2))
if RegisterType.PCICFG == rtype or RegisterType.MMCFG == rtype:
b = int(reg['bus'],16)
d = int(reg['dev'],16)