Commit Graph

1484 Commits

Author SHA1 Message Date
Dan Scott abd75bd474 replace error() with log_error() 2022-05-18 16:26:45 -07:00
Dan Scott 2d56c7fe5f update confirmation input logic 2022-05-18 16:26:45 -07:00
Dan Scott bc723962b1 remove import statements 2022-05-18 16:26:45 -07:00
Dan Scott 2a9ab773ae update copyright years 2022-05-18 16:26:45 -07:00
Dan Scott 460fb6c4e0 replace cs_input() with input(), code cleanup 2022-05-18 16:26:45 -07:00
Frinzell, Aaron 710fdc4965 Update find_EFI_Table() in uefi.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 16:23:14 -07:00
Frinzell, Aaron 4a82a27d3d Add ref and clean up Interpreting-Results.rst
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 16:22:13 -07:00
Frinzell, Aaron eb49eea59a Update get_device_bus() behavior in chipset.py and hal/mmio.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 16:17:04 -07:00
Stanley Chang e3a1b7fe6a Fix is_supported in smm_dma
This patch fixes the condition-checking logic in smm_dma.py

Signed-off-by: Stanley Chang <stanley.chang@intel.com>
2022-05-18 15:09:43 -07:00
Frinzell, Aaron b3541214c5 Update is_supported() in sgx_check.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 14:52:25 -07:00
Frinzell, Aaron 2351623241 Update is_supported() in spi_desc.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 14:18:01 -07:00
Frinzell, Aaron 993c05f76a Update is_supported() in spi_access.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 13:15:38 -07:00
Frinzell, Aaron 2f988ad1c4 Update AUTHORS for 1.8.4
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 13:14:24 -07:00
Sara Batllori 1e528be6d1 Add changes to improve documentation
Signed-off-by: Sara Batllori <sara.batllori@intel.com>
2022-05-18 13:14:04 -07:00
Frinzell, Aaron 05e37bb5fb Add Add usage documentation to memconfig.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 13:06:45 -07:00
Frinzell, Aaron 2278150053 Update is_supported() in smrr.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 12:15:20 -07:00
Frinzell, Aaron 59c74b09d1 Update is_supported() in rtclock.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 11:35:42 -07:00
Frinzell, Aaron 043985359c Update is_supported() in remap.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 11:34:06 -07:00
Frinzell, Aaron a26b2bb614 Update is_supported() in spectre_v2.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 11:16:05 -07:00
Frinzell, Aaron 8c0b3f2870 Update is_supported() in ia32cfg.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 10:53:39 -07:00
Frinzell, Aaron f9b2e6a59e Update is_supported() in bios_wp.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 10:46:43 -07:00
Frinzell, Aaron 7a772c0c44 Code clean up in decode_cmd.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 10:10:01 -07:00
Frinzell, Aaron 77c8fff116 Clean up Vulnerabilities-and-CHIPSEC-Modules.rst
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 10:08:41 -07:00
Frinzell, Aaron 1719db9287 Code clean up in scan_blocked.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 10:07:53 -07:00
Frinzell, Aaron 587c1d5df2 Code clean up in reputation.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-18 09:56:05 -07:00
Sara Batllori 4867caa01f Fix GTTMMADR mask for TGLH
Signed-off-by: Sara Batllori <sara.batllori@intel.com>
2022-05-17 15:45:58 -07:00
Frinzell, Aaron b91b3a6b4e header
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-17 15:36:02 -07:00
Frinzell, Aaron 4026e5c3bb Try isatty() in logger.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-17 15:36:02 -07:00
Frinzell, Aaron 907f8e4824 clean up
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-17 15:19:30 -07:00
Frinzell, Aaron 3b8a138e73 Update uuid.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-17 15:19:30 -07:00
Frinzell, Aaron a74806519e Update EFI manual section
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-17 15:19:30 -07:00
Frinzell, Aaron af43a3c141 Move Py368 EFI to latest EDK2
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-05-17 15:19:30 -07:00
Dan Scott 8878dbefb2 add missing public skus to adl config 2022-05-02 11:44:06 -05:00
Frinzell, Aaron 80676cfff9 Manual
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
1.8.4
2022-04-27 18:00:16 -05:00
Frinzell, Aaron 61219641ee Update to 1.8.4
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 18:00:16 -05:00
startergo 0b5aa8837f Update sign64_sys.bat
Update sign server.
2022-04-27 15:27:05 -05:00
startergo b7d969fb86 Update sign64_sys.bat
Update path
2022-04-27 15:27:05 -05:00
Dan Scott 73238999bd Remove uneeded line 2022-04-27 13:12:14 -07:00
Dan Scott 45d95c74c8 Add config file for AlderLake platforms 2022-04-27 13:12:14 -07:00
Frinzell, Aaron a70bc0bd9c Add usage documentation to spi_desc.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:10:55 -07:00
Frinzell, Aaron f218d88f21 Add is_supported() comment
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:10:29 -07:00
Frinzell, Aaron eb5b150a17 Add usage documentation to bios_smi.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:10:29 -07:00
Frinzell, Aaron 21721eeedd Add usage documentation to ia32cfg.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:08:10 -07:00
Frinzell, Aaron 487405eea1 Update is_supported() in smm_dma.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 10:52:09 -05:00
Nicolas Iooss 202de615f3 hal/iommu: do not raise exception when an IOMMU BAR is not configured
On some testing systems, `chipsec_util.py iommu config` fails with:

    [CHIPSEC] Executing command 'iommu' with args ['config']

    [CHIPSEC] Couldn't find DMAR ACPI table

    ==================================================================
    [iommu] GFXVTD IOMMU Engine Configuration
    ==================================================================
    Base register (BAR)       : GFXVTBAR
    BAR register value        : 0x0
    Traceback (most recent call last):
      File "./chipsec_util.py", line 236, in <module>
        sys.exit(main())
      File "./chipsec_util.py", line 232, in main
        return chipsecUtil.main()
      File "./chipsec_util.py", line 204, in main
        comm.run()
      File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 139, in run
        self.func()
      File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 122, in iommu_config
        self.iommu_engine('config')
      File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 114, in iommu_engine
        if   (cmd == 'config' ): _iommu.dump_IOMMU_configuration( e )
      File "/root/chipsec/chipsec/hal/iommu.py", line 78, in dump_IOMMU_configuration
        base    = self.get_IOMMU_Base_Address( iommu_engine )
      File "/root/chipsec/chipsec/hal/iommu.py", line 52, in get_IOMMU_Base_Address
        (base, size) = self.mmio.get_MMIO_BAR_base_address(vtd_base_name)
      File "/root/chipsec/chipsec/hal/mmio.py", line 249, in get_MMIO_BAR_base_address
        raise CSReadError('[mmio] Base address was determined to be 0')
    chipsec.exceptions.CSReadError: [mmio] Base address was determined to be 0

Indeed, the OS did not configure any IOMMU and GFXVTBAR was zero. It is
nonetheless annoying that the execution of this utility stops without
describing the other IOMMU ("VTBAR").

Fix this issue by returning early from the dump functions if the BAR
contains zero. With this change:

    $ ./chipsec_util.py iommu config
    ...
    ==================================================================
    [iommu] GFXVTD IOMMU Engine Configuration
    ==================================================================
    Base register (BAR)       : GFXVTBAR
    BAR register value        : 0x0
    ==================================================================
    [iommu] VTD IOMMU Engine Configuration
    ==================================================================
    Base register (BAR)       : VTBAR
    BAR register value        : 0x0

    $ ./chipsec_util.py iommu status
    ...
    ==================================================================
    [iommu] GFXVTD IOMMU Engine Status:
    ==================================================================
    [iommu] GFXVTBAR value is zero
    ==================================================================
    [iommu] VTD IOMMU Engine Status:
    ==================================================================
    [iommu] VTBAR value is zero

    $ ./chipsec_util.py iommu pt
    ...
    [iommu] GFXVTBAR value is zero
    [iommu] VTBAR value is zero

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-04-27 10:51:21 -05:00
Frinzell, Aaron a0a1df5183 add line
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 10:44:35 -05:00
Frinzell, Aaron a40b499515 Add cli options text to pcie_fuzz.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 10:44:35 -05:00
Frinzell, Aaron 67f0aba857 Update is_suported() in bios_ts.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:05:06 -05:00
Sara Batllori 8ad4185bec Fix sphinx warnings and index version overwrite 2022-04-25 17:04:39 -05:00
Frinzell, Aaron 1da846086f remove comment
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:04:27 -05:00