1392 Commits

Author SHA1 Message Date
Nathaniel Mitchell 1d6a2668d5 Update to 1.8.2
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1.8.2
2022-03-01 13:44:21 -08:00
Nicolas Iooss 88d185e33f Add a command to dump Intel TXT public registers
Provide a way to dump the content of all TXT registers.
Here is an example of output:

    $ ./chipsec_util.py txt state

    ################################################################
    ##                                                            ##
    ##  CHIPSEC: Platform Hardware Security Assessment Framework  ##
    ##                                                            ##
    ################################################################
    [CHIPSEC] Version : 1.8.1
    [CHIPSEC] OS      : Linux 5.16.5-arch1-1 #1 SMP PREEMPT Tue, 01 Feb 2022 21:42:50 +0000 x86_64
    [CHIPSEC] Python  : 3.10.2 (64-bit)

    ****** Chipsec Linux Kernel module is licensed under GPL 2.0
    [CHIPSEC] API mode: using CHIPSEC kernel module API
    [CHIPSEC] Helper  : LinuxHelper (/mnt/data/to-be-backed-up/projects/chipsec/drivers/linux/chipsec.ko)
    [CHIPSEC] Platform: Desktop 6th Generation Core Processor Quad Core (Skylake CPU / Sunrise Point PCH)
    [CHIPSEC]      VID: 8086
    [CHIPSEC]      DID: 191F
    [CHIPSEC]      RID: 07
    [CHIPSEC] PCH     : Intel H170 (100 series) PCH
    [CHIPSEC]      VID: 8086
    [CHIPSEC]      DID: A144
    [CHIPSEC]      RID: 31
    [CHIPSEC] Executing command 'txt' with args ['state']

    [CHIPSEC] CPUID.01H.ECX[Bit 6] = 1 << Safer Mode Extensions (SMX)
    [CHIPSEC] CPUID.01H.ECX[Bit 5] = 1 << Virtual Machine Extensions (VMX)
    [CHIPSEC] CR4.SMXE[Bit 14] = 0 << Safer Mode Extensions Enable
    [CHIPSEC] CR4.VMXE[Bit 13] = 0 << Virtual Machine Extensions Enable
    [CHIPSEC] IA32_FEATURE_CONTROL = 0x00000005 (Processor Feature Control)
    [CHIPSEC]     [00] LOCK                    = 1 << Lock
    [CHIPSEC]     [01] EN_VMX_INSIDE_SMX       = 0 << Enable VMX inside SMX operation
    [CHIPSEC]     [02] EN_VMX_OUTSIDE_SMX      = 1 << Enable VMX outside SMX operation
    [CHIPSEC]     [03] Reserved0               = 0 << Reserved
    [CHIPSEC]     [08] SENTER_LOCAL_EN         = 0 << SENTER Local Functions Enable
    [CHIPSEC]     [15] SENTER_GLOBAL_EN        = 0 << SENTER Global Enable
    [CHIPSEC]     [16] Reserved1               = 0 << Reserved
    [CHIPSEC]     [17] SGX_LAUNCH_CTRL_EN      = 0 << SGX Launch Control Enable
    [CHIPSEC]     [18] SGX_GLOBAL_EN           = 0 << SGX Global Enable
    [CHIPSEC]     [19] Reserved2               = 0 << Reserved
    [CHIPSEC]     [20] LMCE_ON                 = 0 << Turn Local Machine Check On
    [CHIPSEC]
    [CHIPSEC] TXT_DIDVID = 0x00000001B0068086 (TXT Device ID, at FED30110)
    [CHIPSEC]     [00] VID                     = 8086 << Vendor ID
    [CHIPSEC]     [16] DID                     = B006 << Device ID
    [CHIPSEC]     [32] RID                     = 1 << Revision ID
    [CHIPSEC]     [48] EXTID                   = 0 << Extended ID
    [CHIPSEC]
    [CHIPSEC] TXT Public Key Hash: 2d67ddd75ef9339266a56f27189555ae77a2b0de774222e5de248dbeb8e33dd7
    [CHIPSEC] Public Key Hash in MSR[0x20...0x23]: c14a4b4be9b8aa001b65377fe689d252e6c68dcd66d37bce1da9769867d10cfd
    [CHIPSEC]
    [CHIPSEC] TXT_STS = 0x0000000000000002 (TXT Status, at FED30000)
    [CHIPSEC]     [00] SENTER_DONE_STS         = 0 << SENTER Done
    [CHIPSEC]     [01] SEXIT_DONE_STS          = 1 << SEXIT Done
    [CHIPSEC]     [04] MEM_UNLOCK_STS          = 0 << Memory Unlocked
    [CHIPSEC]     [06] MEM_CONFIG_LOCK_STS     = 0 << Memory Configuration Locked
    [CHIPSEC]     [07] PRIVATE_OPEN_STS        = 0 << Open-Private Command Performed
    [CHIPSEC]     [10] NTP_ENABLE_STS          = 0 << NTP Enabled
    [CHIPSEC]     [11] MEM_CONFIG_OK_STS       = 0 << Mem CFG OK
    [CHIPSEC]     [12] PMRC_LOCK_STS           = 0 << PMRC Locked
    [CHIPSEC]     [13] SMM_OPEN_STS            = 0 << SMM Opened
    [CHIPSEC]     [14] TXT_LOCALITY3_OPEN_STS  = 0 << Locality 3 Opened
    [CHIPSEC]     [15] TXT_LOCALITY1_OPEN_STS  = 0 << Locality 1 Opened
    [CHIPSEC]     [16] TXT_LOCALITY2_OPEN_STS  = 0 << Locality 2 Opened
    [CHIPSEC] TXT_ESTS = 0x0000000000000000 (TXT Error Status, at FED30008)
    [CHIPSEC]     [00] TXT_RESET_STS           = 0 << TXT Reset
    [CHIPSEC]     [01] ROGUE_STS               = 0 << Rogue Status
    [CHIPSEC]     [06] WAKE_ERROR_STS          = 0 << Wake Error
    [CHIPSEC] TXT_E2STS = 0x0000000000000004 (TXT Extended Error Status, at FED308F0)
    [CHIPSEC]     [01] SECRETS_STS             = 0 << Secrets in Memory
    [CHIPSEC] TXT_ERRORCODE = 0x0000000000000000 (TXT Error Code (0xC0000001 when successful SINIT), at FED30030)
    [CHIPSEC]     [00] TYPE2_MODULE_TYPE       = 0 << Module Type (0 for BIOS ACM, 1 for SINIT)
    [CHIPSEC]     [04] TYPE2_CLASS_CODE        = 0 << Class Code
    [CHIPSEC]     [10] TYPE2_MAJOR_ERROR_CODE  = 0 << Major Error Code
    [CHIPSEC]     [15] SOFTWARE_SOURCE         = 0 << Software Source (0 for ACM, 1 of MLE)
    [CHIPSEC]     [16] TYPE1_MINOR_ERROR_CODE  = 0 << Minor Error Code
    [CHIPSEC]     [28] TYPE1_RESERVED          = 0 << Failure Condition Details
    [CHIPSEC]     [30] SOFTWARE                = 0 << Error reported by Software (0 for Processor)
    [CHIPSEC]     [31] VALID                   = 0 << Valid Register Content
    [CHIPSEC]
    [CHIPSEC] TXT_SPAD = 0x0000000000000000 (Boot Status, at FED300A0)
    [CHIPSEC]     [00] ACM_INTERNAL            = 0 << ACM Internal Use
    [CHIPSEC]     [30] TXT_STARTUP_SUCCESS     = 0 << TXT Startup Success
    [CHIPSEC]     [31] BOOT_STATUS             = 0 << General Startup ACM to BIOS status communication
    [CHIPSEC]     [47] MEM_POWER_DOWN_EXECUTED = 0 << Memory content was cleared via power down
    [CHIPSEC]     [48] BOOT_STATUS_DETAILS_48  = 0 << Startup ACM to BIOS communication in MP platforms
    [CHIPSEC]     [53] TXT_POLICY_ENABLE       = 0 << Startup ACM indication of run-time enabled status of TXT
    [CHIPSEC]     [54] BOOT_STATUS_DETAILS_54  = 0 << Startup ACM to BIOS communication in MP platforms
    [CHIPSEC]     [59] BIOS_TRUSTED            = 0 << BIOS is trusted
    [CHIPSEC]     [60] TXT_POLICY_DISABLE      = 0 << TXT has been disabled by runtime FIT type 0xA record policy setting
    [CHIPSEC]     [61] BOOT_STATUS_DETAILS_61  = 0 << Startup ACM to BIOS communication in MP platforms
    [CHIPSEC]     [62] CPU_ERROR               = 0 << ACM authentication error
    [CHIPSEC]     [63] S_ACM_SUCCESS           = 0 << S-ACM successfully enforced its logic for all provisioned technologies
    [CHIPSEC] TXT_ACM_STATUS = 0x00000000 (TXT ACM Status, at FED30328)
    [CHIPSEC]     [00] MODULE_TYPE             = 0 << Module Type
    [CHIPSEC]     [04] CLASS_CODE              = 0 << Class Code
    [CHIPSEC]     [10] MAJOR_ERROR_CODE        = 0 << Major Error Code
    [CHIPSEC]     [15] ACM_STARTED             = 0 << ACM Started
    [CHIPSEC]     [16] MINOR_ERROR_CODE        = 0 << Minor Error Code
    [CHIPSEC]     [31] VALID                   = 0 << Valid
    [CHIPSEC] TXT_FIT = 0x00000000 (FIT (Firmware Interface Table), at FED30340)
    [CHIPSEC]     [00] FIT_FAILED              = 0 << FIT Failed
    [CHIPSEC]     [01] S_ACM_FAILED            = 0 << S-ACM Failed
    [CHIPSEC]     [02] FIT_MEASURED            = 0 << FIT Measured
    [CHIPSEC]     [03] FIT_FALLBACK            = 0 << FIT Fallback
    [CHIPSEC] TXT_SCRATCHPAD = 0x0000000000000000 (ACM Policy Status, at FED30378)
    [CHIPSEC]     [13] TPM_TYPE                = 0 << TPM type detected by Startup ACM (0 for no TPM, 1 for dTPM1.2, 2 for dTPM2.0, 3 for PTT)
    [CHIPSEC]     [15] TPM_SUCCESS             = 0 << TPM Success
    [CHIPSEC]     [17] BOOT_POLICIES_2         = 0 << Boot Policies
    [CHIPSEC]     [18] BACKUP_ACTION           = 0 << Backup Action
    [CHIPSEC]     [20] TXT_PROFILE             = 0 << TXT Profile
    [CHIPSEC]     [25] MEMORY_SCRUB_POLICY     = 0 << Memory Scrub Policy
    [CHIPSEC]     [29] IBB_DMA_PROTECTION      = 0 << IBB (Initial Boot Block) DMA Protection
    [CHIPSEC]     [32] S_CRTM_STATUS           = 0 << Startup ACM S-CRTM establishment
    [CHIPSEC]     [35] CPU_COSIGNING_ENABLE    = 0 << CPU co-signing enabled
    [CHIPSEC]     [36] TPM_STARTUP_LOCALITY    = 0 << Locality at which TPM2_Startup command was executed (0 for locality 3, 1 for locality 0)
    [CHIPSEC]
    [CHIPSEC] TXT_SINIT_BASE = 0x00000000 (SINIT Base Address, at FED30270)
    [CHIPSEC] TXT_SINIT_SIZE = 0x00000000 (SINIT Size, at FED30278)
    [CHIPSEC] TXT_MLE_JOIN = 0x00000000 (MLE Join Base Address, at FED30290)
    [CHIPSEC] TXT_HEAP_BASE = 0x00000000 (TXT Heap Base Address, at FED30300)
    [CHIPSEC] TXT_HEAP_SIZE = 0x00000000 (TXT Heap Size, at FED30308)
    [CHIPSEC] TXT_MSEG_BASE = 0x00000000 (TXT MSEG Base Address, at FED30310)
    [CHIPSEC] TXT_MSEG_SIZE = 0x00000000 (TXT MSEG Size, at FED30318)
    [CHIPSEC]
    [CHIPSEC] TXT_DPR = 0x00000000 (TXT DMA Protected Range (deprecated, replaced by PCI0.0.0_DPR), at FED30330)
    [CHIPSEC]     [00] LOCK                    = 0 << Lock Bits 19:0
    [CHIPSEC]     [04] SIZE                    = 0 << Protected Memory Size (in MB)
    [CHIPSEC]     [20] TOP                     = 0 << Top Address+1 of DPR (base of TSEG)
    [CHIPSEC] TXT_VER_FSBIF = 0xFFFFFFFF (TXT Front Side Bus Interface, at FED30100)
    [CHIPSEC]     [31] DEBUG_FUSE              = 1 << Chipset is Production Fused (0 for Debug)
    [CHIPSEC] TXT_VER_QPIIF = 0x9D003000 (TXT Intel QuickPath Interconnect Interface, at FED30200)
    [CHIPSEC]     [19] PMRC_CAPABLE            = 0 << PMRC Capable
    [CHIPSEC]     [26] DPR_CAPABLE             = 1 << DPR Capable
    [CHIPSEC]     [31] DEBUG_FUSE              = 1 << Chipset is Production Fused (0 for Debug)
    [CHIPSEC] TXT_PCH_DIDVID = 0x00000001A1448086 (TXT Platform Controller Hub Device ID, at FED30810)
    [CHIPSEC]     [00] VID                     = 8086 << Vendor ID
    [CHIPSEC]     [16] DID                     = A144 << Device ID
    [CHIPSEC]     [32] RID                     = 1 << Revision ID
    [CHIPSEC] INSMM = 0x00000000 (InSMM.STS, at FED30880)
    [CHIPSEC]     [00] STS                     = 0 << BIOS Write Enable when enabled by SPI.BC.EISS=1

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-02-28 15:49:48 -08:00
Nicolas Iooss e4e88dd5dc Intel TXT: add several registers in the fed30000 memory area
Several registers from an old version of TXT were documented in an
"Intel® Trusted Execution Technology (Intel®TXT) LAB Handout" from 2010:
https://docplayer.net/42821782-Intel-trusted-execution-technology-intel-txt-lab-handout.html

This includes MSEG definition, which was also documented in tboot:
https://github.com/tklengyel/tboot/blob/c9ca81f41b4a3eaa8e00c12a3d1d6d3c783782d4/tboot/include/txt/config_regs.h

    #define TXTCR_MSEG_BASE             0x0310
    #define TXTCR_MSEG_SIZE             0x0318

Moreover, add registers from Intel TXT Software Development Guide 315168-017
(updated in January 2021) from
http://www.intel.com/content/dam/www/public/us/en/documents/guides/intel-txt-software-development-guide.pdf

Add TXT_ACM_STATUS from 9elements/converged-security-suite repository
https://github.com/9elements/converged-security-suite/commit/b5037f9c93701d52fe4f3beb4b44a65854479609
and slimbootloader project
https://github.com/slimbootloader/slimbootloader/blob/35813687fb2a69a70727f82b7ed125fc2b22d35b/Platform/CometlakevBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
and coreboot project
https://github.com/coreboot/coreboot/blob/28894c57988076688395c8a122d79640a3702d1a/src/security/intel/cbnt/cbnt.h
2022-02-28 15:49:48 -08:00
Nicolas Iooss 5651a0d3ac Intel TXT: add InSMM.STS bit definition
Several sources of information documents the first bit of 0xFED30880 to
be "InSMM.STS":

- Some PCH datasheet from
  https://www.intel.fr/content/www/fr/fr/products/docs/processors/core/core-technical-resources.html
  document the bit 5 of register BIOS_SPI_BC as:

    Enable InSMM.STS (EISS): When this bit is set, the BIOS region is
    not writable until the CPU sets the InSMM.STS bit.
    If this bit [5] is set, then WPD must be a '1' and
    InSMM.STS(0xFED3_0880[0]) must be '1' also in order to write to
    BIOS region of SPI Flash.
    If this bit [5] is clear, then the InSMM.STS is a do not care.
    This bit is locked by LE.

  (chipsec already defines this bit in pch_c620.xml, and it is named
  SMM_BWP in other pch_...xml files)

- Support for this bit was added in coreboot:
  https://review.coreboot.org/c/coreboot/+/51796/14
- Support for this bit was added in the EDK II project:
  https://github.com/tianocore/edk2-platforms/commit/17f047154203c73065dcdad8b6a2c59460bf2f53

Enable to easy access this bit by definining an INSMM register.
2022-02-28 15:49:48 -08:00
Nicolas Iooss 01906dc1bf Intel TXT: fix ERRORCODE.VALID bit definition 2022-02-28 15:49:48 -08:00
Mathias Krause 81fa32bd7e drivers/linux: enforce address requirement for IOCTL_ALLOC_PHYSMEM
Try harder to fulfill the physical address constraint for the
IOCTL_ALLOC_PHYSMEM ioctl by trying to allocate memory from the zones
that fit the maximum address best, but fall-back to the normal zone in
case the allocation fails.

If we fail to allocate memory that fulfills the maximum physical address
constraint, make the ioctl() fail as well instead of emitting a warning.

This is safer then making, e.g., the tools.smm.smm_ptr module corrupt
unrelated memory just because the allocation happens to be above 4GB but
the pointer passed to SMM is truncated to 32 bit.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-28 15:39:19 -08:00
Mathias Krause b7cbbd2712 drivers/linux: merge {read,write}_mem()
With the addition of a bounce buffer both functions are nearly
identical. They only differ in the direction of copy.

Merge them into a common helper function that gets the copy direction
passed as an argument.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-28 15:39:19 -08:00
Mathias Krause eb89b9c248 drivers/linux: add bounce buffer handling to write_mem()
If we try to write to an address that's not allowed by USERCOPY, the
copy will fail.

Use a bounce buffer to work around that, just like read_mem() does.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-28 15:39:19 -08:00
Mathias Krause a687d9e73b drivers/linux: reject invalid addresses in IOCTL_VA2PA
If we get passed an invalid virtual address, make IOCTL_VA2PA fail
instead of returning a bogus address.

Also simplify the code. No need to use 'PHYSICAL_ADDRESS' here,
'phys_addr_t' is just fine.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-28 15:39:19 -08:00
Mathias Krause 62394b6c1c helper/linux: va2pa - handle ioctl() errors
Handle translation errors in ioctl(IOCTL_VA2PA) gracefully to avoid
throwing an exception.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-28 15:39:19 -08:00
Mathias Krause edc4545c8f hal: va2pa - handle translation errors gracefully
If the helper specific va2p() method fails, we shouldn't try to print
'pa' as it might be 'None'.

Swap the error handling with the 'VA -> PA' debug message to avoid
generating a format exception in this case.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-28 15:39:19 -08:00
Nathaniel Mitchell 15294ef53f Fix bug in is_all_ones when passing size as string from xml config
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
2022-02-28 14:34:54 -08:00
Frinzell, Aaron 101729a562 Update vid also
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-02-28 14:25:26 -08:00
Frinzell, Aaron 6c3f10ab82 Better device parsing in multi-bus
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-02-28 14:25:26 -08:00
Frinzell, Aaron d27a5ddfce Check control return values in bios_ts.py 2022-02-25 13:38:13 -08:00
Frinzell, Aaron 672d57f595 Change inputs 2022-02-25 13:37:31 -08:00
Frinzell, Aaron 91b7cab442 Add routine for control 0xff checks 2022-02-25 13:37:31 -08:00
Erik Bjorge c570001e9b Multi-Bus updates
* Allow duplicate PCI device names to map to the same function.
* Update PCI device bus entries to point to a valid bus based on PCI
  enumeration.

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2022-02-25 13:36:49 -08:00
Frinzell, Aaron 95f757ed20 Clairify uefivar_fuzz.py documentation 2022-02-24 17:05:05 -08:00
Erik Bjorge 90fc2bec0c Fixed exception if size attribute is missing
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2022-02-16 08:27:08 -08:00
Nicolas Iooss 7fb6448aec Fix TPM 1.2 commands logging
When running `chipset_util.py tpm pcrread 0 8` to read a PCR (for
example) on a system using a TPM 1.2, the following result is displayed:

    [CHIPSEC] Executing command 'tpm' with args ['command', 'pcrread', '0', '8']

    ----------------------------------------------------------------
                         TPM response header
    ----------------------------------------------------------------
       Response TAG: 0xc4
       Data Size   : 0x1e
       Return Code : 0x0
            Success

    62 79 74 65 61 72 72 61 79 28 62 27 5C 78 30 30 | bytearray(b'\x00
    5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
    5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
    5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
    5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
    5C 78 30 30 5C 78 30 30 5C 78 30 30 27 29       | \x00\x00\x00')

Instead of displaying a hexdump of a Python representation of a
bytearray, display the hexdump of the bytes.

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-02-16 08:24:47 -08:00
Nicolas Iooss 643306766e Add FORCE in Linux driver Makefile
Since Linux 5.15 (commit
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e1f86d7b4b2a5213b012c2b4fe3e5b6ad537686e
), `make` now warns about missing `FORCE` prerequisite:

    /var/lib/dkms/chipsec/1.8.1/build/Makefile:39: FORCE prerequisite
    is missing

Fix this issue by adding the required prerequisite.

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-02-16 08:24:33 -08:00
Nicolas Iooss cebf53dee5 Configure GitHub Actions to stay on Windows Server 2019 for now
GitHub recently upgraded their `windows-latest` environment to Windows
Server 2022:
https://github.blog/changelog/2022-01-11-github-actions-jobs-running-on-windows-latest-are-now-running-on-windows-server-2022/

This environment includes Visual Studio 2022 (cf.
https://github.com/actions/virtual-environments/blob/7f1bc9ed1e3cff016136346e8f12eec301c6c11f/images/win/Windows2022-Readme.md#visual-studio-enterprise-2022
), which is currently not supported by the WDK (Windows Driver Kit):
https://docs.microsoft.com/en-us/windows-hardware/drivers/download-the-wdk#download-and-install-the-windows-11-wdk

Because of this incompatibility, force the workflows to stay on Windows
Server 2019 environments for now.

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-02-16 08:24:09 -08:00
Frinzell, Aaron 244cfa80dc Mem update and log alignment 2022-02-16 08:23:32 -08:00
Frinzell, Aaron 3f3815556b Update write_mmio_reg() in efihelper.py 2022-02-16 08:23:32 -08:00
Erik Bjorge 81083bca03 Flake8 Cleanup
- Remove unused imports
- Improve spacing of functions/methods for readability
- Indentation updates
- Exception expression updates

Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2022-02-16 08:23:01 -08:00
Mathias Krause 3bcc686023 drivers/windows: simplify _swsmi() and fix comments
Drop the unneded register preserving of RBX, RSI and RDI. It's no longer
needed since commit 5c943b8f38 ("Changes to windows helper and driver
to support return values") refactored the code to just work with the
passed SMI_CTX buffer as scratch space.

Also clobber only the lower 16 bits of RAX with 'smi_code_data', as
documented and assumed by callers.

Last, but not least, drop the misleading comment about clobbering DX as
that doesn't happen any more. Also update all other comments to mirror
the current implementation.

This brings the Windows implementation in line with the Linux one.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause af08f9cd93 drivers/linux: make more symbols static
chipsec_km.c is mostly self-contained and thereby has no need to export
symbols.

Make almost all of them 'static' and leave only the (config dependent)
unused ones non-static.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause 2a162c1efa drivers/linux: fix memory leak for IOCTL_ALLOC_PHYSMEM ioctl
If we fail to allocate memory for chaining the user requested allocation
to our accounting list, we leak 'va.'

Fix that. Also fix the return code to be -ENOMEM instead of -EFAULT for
failing memory allocations.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause 07f91de154 drivers/linux: handle xlate errors
In case my_xlate_dev_mem_ptr() fails for a given physical address, we
should return an error instead of trying to read/write to NULL.

Also fix whitespace issues around this code section.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause c80528e0a0 drivers/linux: make symbol search work with -freorder-functions
Commit 397b1b8d8b ("drivers/linux: simplify and fix symbol resolving
for kernels >= 5.10") introduced a method for finding the address of
kallsyms_lookup_name() by scanning kernel code around 'sprint_symbol.'
However, it only looked "backwards" which would be fine, as
kallsyms_lookup_name() gets defined before sprint_symbol() in
kallsyms.c. However, gcc's '-freorder-functions' (which is enabled by
default at -O2 / -Os) may put kallsyms_lookup_name() *after*
sprint_symbol() in the object file, making our search fail to find it.

Account for that and search around sprint_symbol() in both directions.
32kB is more than enough to cover all of kallsyms.o.

Fixes: 397b1b8d8b ("drivers/linux: simplify and fix symbol resolving for kernels >= 5.10")
Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause d471f01dda drivers/linux: grsecurity compatibility for symbol resolving
grsecurity kernels stub out the kallsyms family of functions when the
feature CONFIG_GRKERNSEC_HIDESYM is enabled. This destroys out attempt
to find the address of 'kallsyms_lookup_name' via sprint_symbol().

Prevent that by making use of the '__INCLUDED_BY_HIDESYM' define
grsecurity provides for this exact purpose.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause cbe7bc39a5 drivers/linux: simplify __swsmi__()
The current implementation of __swsmi__ for x86-64 is rather complicated
as it uses more registers than needed. Simplyfy it.

We can use the passed SMI_CTX buffer as scratch space without the need
to use intermediate registers (beside for RDI, for which we use R10 -- a
callee clobbered register).

Bring the implementation more in line with its OS X counterpart and
adapt the comments and code to reflect reality, namely:
- change the C type members to mirror the used (and intended) registers,
- mark the registers as in/out parameters in the comments,
- drop the bogus comment about clobbering DX, as we don't do that and
- fix and tweak the comment about split i/o because of picky firmwares.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause d89210f5b4 helper/linux: don't unnecessary (un)load the kernel module
When the kernel module is already loaded, don't unload and try to load
it again.

This is not only useful during development where one might change the
kernel module code often and load it manually but also for setups that
lift the strict access restrictions to /dev/chipsec, e.g. to allow a
non-root group access to its interface.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Mathias Krause b54990274e .gitignore: ignore in-tree Linux kernel driver build artefacts
During development one might build the driver at its source location.
Add the build artefacts to the git ignore list to make `git status` less
noisy.

Signed-off-by: Mathias Krause <minipli@grsecurity.net>
2022-02-16 08:22:33 -08:00
Nathaniel Mitchell 6172ebe003 Remove google group mailing list 2022-02-09 16:38:01 -08:00
Erik Bjorge 400f8e87a5 Fix regex reference
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2022-02-08 11:06:14 -08:00
Erik Bjorge b131fdc78a Remove import debug code
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2022-02-08 11:06:04 -08:00
Nathaniel Mitchell 130309880f Update to 1.8.1
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
1.8.1
2022-02-01 15:06:09 -08:00
Sae86 c468134d5d Fix version update for index.rst
Signed-off-by: Sae86 <sara.batllori@intel.com>
2022-02-01 11:29:13 -08:00
Frinzell, Aaron 0be5bed8ac Add usage documentation to smm_code_chk.py 2022-02-01 08:37:28 -08:00
Frinzell, Aaron ab54329bc3 Add usage documentation to spi_access.py 2022-02-01 08:16:32 -08:00
Frinzell, Aaron f4f196b47f Add usage documentation to sgx_check.py 2022-02-01 08:14:19 -08:00
Aaron Frinzell 28a5234170 Add routines to check for all 1's (0xFs) 2022-01-31 10:12:06 -08:00
Nicolas Iooss 8fd2f42b9d Add registers for Intel TXT (Trusted Execution Technology)
When studying Intel TXT, it is quite helpful to be able to directly read
the content of some registers such as TXT.ERRORCODE and TXT.DIDVID.

Create a new configuration file with registers from a guide which was
initially published on
https://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-01-31 10:11:41 -08:00
brentholtsclaw 67f5f9ca43 Display correct thread when printing (smm_code_chk)
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2022-01-31 09:04:58 -08:00
net-wayfarer 463281907c [DKMS] Remove deprecated REMAKE_INITRD flag.
DKMS upstream has deprecated this flag;
https://github.com/dell/dkms/commit/961f9ceac4cf6772cb4c52bf4836a0f6c9818239
This PR removes the deprecated flag, which would otherwise generate a warning
whenever dkms is invoked.

Further, prior to this PR the flag was set to 'off'.
2022-01-28 11:07:08 -08:00
brentholtsclaw 64beb99e1d Update commments to match changes
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2022-01-28 10:52:09 -08:00
BrentHoltsclaw 6d63af8cee Update cpu.asm
update per comments
2022-01-28 10:52:09 -08:00
brentholtsclaw 3af284e1bd update send_SMI_APMC command to split 0xB2 and 0xB3
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2022-01-28 10:52:09 -08:00