1451 Commits

Author SHA1 Message Date
Frinzell, Aaron 80676cfff9 Manual
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
1.8.4
2022-04-27 18:00:16 -05:00
Frinzell, Aaron 61219641ee Update to 1.8.4
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 18:00:16 -05:00
startergo 0b5aa8837f Update sign64_sys.bat
Update sign server.
2022-04-27 15:27:05 -05:00
startergo b7d969fb86 Update sign64_sys.bat
Update path
2022-04-27 15:27:05 -05:00
Dan Scott 73238999bd Remove uneeded line 2022-04-27 13:12:14 -07:00
Dan Scott 45d95c74c8 Add config file for AlderLake platforms 2022-04-27 13:12:14 -07:00
Frinzell, Aaron a70bc0bd9c Add usage documentation to spi_desc.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:10:55 -07:00
Frinzell, Aaron f218d88f21 Add is_supported() comment
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:10:29 -07:00
Frinzell, Aaron eb5b150a17 Add usage documentation to bios_smi.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:10:29 -07:00
Frinzell, Aaron 21721eeedd Add usage documentation to ia32cfg.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 13:08:10 -07:00
Frinzell, Aaron 487405eea1 Update is_supported() in smm_dma.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 10:52:09 -05:00
Nicolas Iooss 202de615f3 hal/iommu: do not raise exception when an IOMMU BAR is not configured
On some testing systems, `chipsec_util.py iommu config` fails with:

    [CHIPSEC] Executing command 'iommu' with args ['config']

    [CHIPSEC] Couldn't find DMAR ACPI table

    ==================================================================
    [iommu] GFXVTD IOMMU Engine Configuration
    ==================================================================
    Base register (BAR)       : GFXVTBAR
    BAR register value        : 0x0
    Traceback (most recent call last):
      File "./chipsec_util.py", line 236, in <module>
        sys.exit(main())
      File "./chipsec_util.py", line 232, in main
        return chipsecUtil.main()
      File "./chipsec_util.py", line 204, in main
        comm.run()
      File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 139, in run
        self.func()
      File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 122, in iommu_config
        self.iommu_engine('config')
      File "/root/chipsec/chipsec/utilcmd/iommu_cmd.py", line 114, in iommu_engine
        if   (cmd == 'config' ): _iommu.dump_IOMMU_configuration( e )
      File "/root/chipsec/chipsec/hal/iommu.py", line 78, in dump_IOMMU_configuration
        base    = self.get_IOMMU_Base_Address( iommu_engine )
      File "/root/chipsec/chipsec/hal/iommu.py", line 52, in get_IOMMU_Base_Address
        (base, size) = self.mmio.get_MMIO_BAR_base_address(vtd_base_name)
      File "/root/chipsec/chipsec/hal/mmio.py", line 249, in get_MMIO_BAR_base_address
        raise CSReadError('[mmio] Base address was determined to be 0')
    chipsec.exceptions.CSReadError: [mmio] Base address was determined to be 0

Indeed, the OS did not configure any IOMMU and GFXVTBAR was zero. It is
nonetheless annoying that the execution of this utility stops without
describing the other IOMMU ("VTBAR").

Fix this issue by returning early from the dump functions if the BAR
contains zero. With this change:

    $ ./chipsec_util.py iommu config
    ...
    ==================================================================
    [iommu] GFXVTD IOMMU Engine Configuration
    ==================================================================
    Base register (BAR)       : GFXVTBAR
    BAR register value        : 0x0
    ==================================================================
    [iommu] VTD IOMMU Engine Configuration
    ==================================================================
    Base register (BAR)       : VTBAR
    BAR register value        : 0x0

    $ ./chipsec_util.py iommu status
    ...
    ==================================================================
    [iommu] GFXVTD IOMMU Engine Status:
    ==================================================================
    [iommu] GFXVTBAR value is zero
    ==================================================================
    [iommu] VTD IOMMU Engine Status:
    ==================================================================
    [iommu] VTBAR value is zero

    $ ./chipsec_util.py iommu pt
    ...
    [iommu] GFXVTBAR value is zero
    [iommu] VTBAR value is zero

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-04-27 10:51:21 -05:00
Frinzell, Aaron a0a1df5183 add line
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 10:44:35 -05:00
Frinzell, Aaron a40b499515 Add cli options text to pcie_fuzz.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-27 10:44:35 -05:00
Frinzell, Aaron 67f0aba857 Update is_suported() in bios_ts.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:05:06 -05:00
Sara Batllori 8ad4185bec Fix sphinx warnings and index version overwrite 2022-04-25 17:04:39 -05:00
Frinzell, Aaron 1da846086f remove comment
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:04:27 -05:00
Frinzell, Aaron 9985c457f6 Add usage documentation to cpuid_fuzz.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:04:27 -05:00
Frinzell, Aaron 89cf732b4b Handle MSR read error in memlock.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:03:35 -05:00
Frinzell, Aaron 4bd01300ba remove comments
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:03:22 -05:00
Frinzell, Aaron 829c3611f2 else new line
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:03:22 -05:00
Frinzell, Aaron 808d05e3e9 Add usage documentation to variables.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:03:22 -05:00
Frinzell, Aaron 7f6a6ac262 Code cleanup in module_common.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:03:00 -05:00
Frinzell, Aaron 2e38de930a spaces
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:49 -05:00
Frinzell, Aaron 6ac4044181 scan_image.py code cleanup
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:49 -05:00
Frinzell, Aaron dae71c282d remove comment section
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:36 -05:00
Frinzell, Aaron 02406ef032 spectre_v2.py code cleanup
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:36 -05:00
Frinzell, Aaron d495371d63 Update usage documentation to vbox_crash_acpibase.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:26 -05:00
Frinzell, Aaron 1692fc71b0 s3script_modify.py code cleanup
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:15 -05:00
Frinzell, Aaron 370f1aba0b logic
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:06 -05:00
Frinzell, Aaron 5e1882ac8a Add usage documentation to cpu_info.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:02:06 -05:00
Frinzell, Aaron 62b3d63d03 End spaces
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:00:20 -05:00
Frinzell, Aaron 0ba38fbcb1 uefivar_fuzz.py minor code cleanup
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:00:20 -05:00
Frinzell, Aaron e06aa2745e Lower case i
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:00:09 -05:00
Frinzell, Aaron ae8349363b Add usage documentation to me_mfg_mode.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 17:00:09 -05:00
Frinzell, Aaron 2be646a63d Add usage documentation to spi_fdopss.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:59:58 -05:00
Frinzell, Aaron e66b1107f7 Add usage documentation to spi_lock.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:59:26 -05:00
Frinzell, Aaron 07fdea7d05 update flag
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:58:52 -05:00
Frinzell, Aaron d63c16caae Update SoC based configs
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:58:52 -05:00
Frinzell, Aaron 10b7ed86dd spaces
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:58:37 -05:00
Frinzell, Aaron 243d4b38ec use tri-state
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:58:37 -05:00
Frinzell, Aaron 5d185f53b0 Test error
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:58:37 -05:00
Frinzell, Aaron 6080321953 Don't check for PCH on SoC
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-04-25 16:58:37 -05:00
Frinzell, Aaron 6f6de3641d Manual 1.8.3
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
1.8.3
2022-03-30 18:22:15 -05:00
Frinzell, Aaron 5b70d7dc4f Updating to 1.8.3
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-03-30 18:22:15 -05:00
Gabriel Kerneis 33b34673b9 Disable colorized output when piping the output or when NO_COLOR is set (#1395)
The former case is useful if the user runs some variant of:
  chipsec_main.py > chipsec.log

The latter case is defined in https://no-color.org/ and simple enough to
implement while we are improving color handling.

Signed-off-by: Gabriel Kerneis <gabriel.kerneis@ssi.gouv.fr>
2022-03-29 17:36:55 -05:00
Aaron Frinzell 2a67e1a24c Correct minor typo in sgx_check.py (#1414)
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-03-28 14:21:24 -07:00
Aaron Frinzell e877ec9073 Fix list-modify-while-iterate bug in bios_wp.py (#1413)
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-03-28 14:18:08 -07:00
Aaron Frinzell b90be4c48d Cleanup and add docstring to pcie_fuzz.py (#1411)
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-03-28 14:16:55 -07:00
Aaron Frinzell 463b09eaac Cleanup and add docstring to wsmt.py (#1410)
* Cleanup and add docstring to wsmt.py

Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>

* TypeError

Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-03-28 14:13:09 -07:00