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CHIPSEC 2.0.0

Nathaniel Mitchell edited this page 2024-12-04 08:44:20 -08:00

Table of Contents

• Changes
• New configurations:
• Register Objects:
• HAL Changes:
• Under consideration:

See branch https://github.com/chipsec/chipsec/tree/dev/chipsec2

A few of the outlined items in previous versions of this wiki page have already been implemented into chipsec 1 and so are not mentioned below.

Changes

New configurations:

• chipsec/cfg/[VID]/[platform]
  • Main platform configuration file. Defines sub-components and which IP xml to use.
• chipsec/cfg/[VID]/[IPFolder]/[IP]
  • IP XML Definition.
• chipsec/cfg/parsers/ip
  • Mapping of XML fields to python objects

Register Objects:

• chipsec/cfg/parsers/registers
  • Register objects, for how to display, read and write a type of register.
• chipsec/library/registers/[RegTypes]
  • Defines how to get the definition (WIP)
• chipsec/library/register
  • All Register Objects are packaged into an "ObjList".
  • To get the ObjList, call chipset.register.get_list_by_name('Fully.qualified.register.name')
    • This will get you all of the registers that have that name. This is helpful if you have multiple devices with the same name and register structure. (eg msr across all threads)
• chipsec/library/control, lock, device
  • Holds a similar structure as the chipsec/library/register. Provides interface to controls, locks and devices.

HAL Changes:

• chipsec/hal/hals
  • This is the object that chipset holds and controls all of the HALs. Performs Dynamic Lazy instantiation of HALs.
• chipsec/hal/[folder]/[hal]
  • Implementation of HAL. Must define a global haldata dictionary variable that has the keys 'arch' (VID that the HAL is for [FFFF for generic]) and 'name' (Class name that is to be passed to Hals Object)

Under consideration:

• Module structure changes to separate AMD and Intel modules, so you don't see Not applicable modules when running on different vendors.