Add additional exception information

Bump icicle version

.cargo/config.toml

@@ -0,0 +1,2 @@
+[env]
+GHIDRA_SRC = { value = "python/icicle", relative = true }

.github/workflows/CI.yml

@@ -2,160 +2,232 @@ name: CI
 
 on: [push, pull_request]
 
+# Automatically cancel previous runs of this workflow on the same branch
+concurrency:
+  group: ${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+
 jobs:
+  linux:
+    # Skip building pull requests from the same repository
+    if: ${{ github.event_name == 'push' || (github.event_name == 'pull_request' && github.event.pull_request.head.repo.full_name != github.repository) }}
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        target: [x86_64, aarch64]
+      fail-fast: false
+    steps:
+      - uses: actions/checkout@v5
+        with:
+          submodules: 'true'
+
+      - name: Update pyproject.toml version
+        if: ${{ startsWith(github.ref, 'refs/tags/') }}
+        shell: bash
+        run: |
+          # Extract version from tag (strip 'v' prefix if present)
+          VERSION=${GITHUB_REF#refs/tags/}
+          VERSION=${VERSION#v}
+          echo "Extracted version: $VERSION"
+          
+          # Update version in pyproject.toml (works on both GNU and BSD sed)
+          sed -i.bak "s/^version = .*/version = \"$VERSION\"/" pyproject.toml
+          rm pyproject.toml.bak
+
+      - name: Install uv
+        uses: astral-sh/setup-uv@v6
+        with:
+          version: "0.9.3"
+
+      # NOTE: On Linux we need to manually export LD_LIBRARY_PATH
+      - name: Set up Python
+        run: |
+          uv python install --default
+          LIBDIR=$(python -c "import sysconfig; print(sysconfig.get_config_var('LIBDIR'))")
+          echo "LD_LIBRARY_PATH=${LIBDIR}:${LD_LIBRARY_PATH}" >> $GITHUB_ENV
+
+      - name: Run Python tests
+        run: uv run pytest -v
+
+      - name: Run Rust tests
+        run: cargo run
+
+      - name: Clean Rust build cache
+        run: cargo clean
+
+      - name: Build wheels
+        uses: PyO3/maturin-action@v1
+        with:
+          target: ${{ matrix.target }}
+          args: --release --out dist --find-interpreter
+          manylinux: auto
+
+      - name: Upload wheels
+        uses: actions/upload-artifact@v4
+        with:
+          name: wheels-linux-${{ matrix.target }}
+          path: dist
+
   windows:
     # Skip building pull requests from the same repository
     if: ${{ github.event_name == 'push' || (github.event_name == 'pull_request' && github.event.pull_request.head.repo.full_name != github.repository) }}
     runs-on: windows-latest
-    env:
-      # Disable output buffering in an attempt to get readable errors
-      PYTHONUNBUFFERED: '1'
     steps:
-      - name: Checkout
-        uses: actions/checkout@v3
+      - uses: actions/checkout@v5
         with:
           submodules: 'true'
-      
-      - name: Python environment
-        uses: actions/setup-python@v4
-        with:
-          python-version: '3.10'
 
-      - name: Install Rust toolchain
-        uses: dtolnay/rust-toolchain@stable
-        with:
-          targets: x86_64-pc-windows-msvc
-
-      - name: Build
+      - name: Update pyproject.toml version
+        if: ${{ startsWith(github.ref, 'refs/tags/') }}
         shell: bash
         run: |
-          pip install -r requirements.txt
-          python setup.py sdist
-          python setup.py bdist_wheel --py-limited-api=cp37
-          pip install --force-reinstall dist/*.whl
-          python -c "import icicle"
+          # Extract version from tag (strip 'v' prefix if present)
+          VERSION=${GITHUB_REF#refs/tags/}
+          VERSION=${VERSION#v}
+          echo "Extracted version: $VERSION"
+          
+          # Update version in pyproject.toml (works on both GNU and BSD sed)
+          sed -i.bak "s/^version = .*/version = \"$VERSION\"/" pyproject.toml
+          rm pyproject.toml.bak
 
-      - name: Test
-        run: |
-          pip install -r tests/requirements.txt
-          python tests/example.py
-          python tests/invalid.py
-    
-      - name: Upload wheels
-        uses: actions/upload-artifact@v3
+      - name: Install uv
+        uses: astral-sh/setup-uv@v7
         with:
-          name: wheels
+          version: "0.9.3"
+
+      - name: Set up Python
+        run: uv python install --default
+
+      - name: Run Rust tests
+        run: cargo run
+
+      - name: Build wheels
+        uses: PyO3/maturin-action@v1
+        with:
+          target: x64
+          args: --release --out dist --find-interpreter
+
+      - name: Run Python tests
+        run: uv run pytest -v
+
+      - name: Upload wheels
+        uses: actions/upload-artifact@v4
+        with:
+          name: wheels-windows-x64
           path: dist
 
   macos:
     # Skip building pull requests from the same repository
     if: ${{ github.event_name == 'push' || (github.event_name == 'pull_request' && github.event.pull_request.head.repo.full_name != github.repository) }}
     runs-on: macos-latest
-    env:
-      # Disable output buffering in an attempt to get readable errors
-      PYTHONUNBUFFERED: '1'
+    strategy:
+      matrix:
+        target: [x86_64, aarch64]
+      fail-fast: false
     steps:
-      - name: Checkout
-        uses: actions/checkout@v3
+      - uses: actions/checkout@v5
         with:
           submodules: 'true'
-      
-      - name: Python environment
-        uses: actions/setup-python@v4
-        with:
-          python-version: '3.10'
 
-      - name: Install Rust toolchain
-        uses: dtolnay/rust-toolchain@stable
-        with:
-          targets: aarch64-apple-darwin, x86_64-apple-darwin
-      
-      - name: Build
+      - name: Update pyproject.toml version
+        if: ${{ startsWith(github.ref, 'refs/tags/') }}
         shell: bash
-        env:
-          DEVELOPER_DIR: /Applications/Xcode.app/Contents/Developer
-          MACOSX_DEPLOYMENT_TARGET: '10.9'
-          ARCHFLAGS: -arch x86_64 -arch arm64
-          PYO3_CROSS_LIB_DIR: /Applications/Xcode.app/Contents/Developer/Library/Frameworks/Python3.framework/Versions/3.9/lib
         run: |
-          pip install -r requirements.txt
-          python setup.py bdist_wheel --py-limited-api=cp37
-          pip install --force-reinstall dist/*_universal2.whl
-          python -c "import icicle"
-      
-      - name: Test
-        run: |
-          pip install -r tests/requirements.txt
-          python tests/example.py
-          python tests/invalid.py
-    
-      - name: Upload wheels
-        uses: actions/upload-artifact@v3
+          # Extract version from tag (strip 'v' prefix if present)
+          VERSION=${GITHUB_REF#refs/tags/}
+          VERSION=${VERSION#v}
+          echo "Extracted version: $VERSION"
+          
+          # Update version in pyproject.toml (works on both GNU and BSD sed)
+          sed -i.bak "s/^version = .*/version = \"$VERSION\"/" pyproject.toml
+          rm pyproject.toml.bak
+
+      - name: Install uv
+        uses: astral-sh/setup-uv@v7
         with:
-          name: wheels
+          version: "0.9.3"
+
+      - name: Set up Python
+        run: uv python install --default
+
+      - name: Run Rust tests
+        if: matrix.target == 'aarch64'
+        run: cargo run --release
+
+      - name: Build wheels
+        uses: PyO3/maturin-action@v1
+        with:
+          target: ${{ matrix.target }}
+          args: --release --out dist --find-interpreter
+
+      - name: Run Python tests
+        if: matrix.target == 'aarch64'
+        run: uv run pytest -v
+
+      - name: Upload wheels
+        uses: actions/upload-artifact@v4
+        with:
+          name: wheels-macos-${{ matrix.target }}
           path: dist
 
-  linux:
+  sdist:
     # Skip building pull requests from the same repository
     if: ${{ github.event_name == 'push' || (github.event_name == 'pull_request' && github.event.pull_request.head.repo.full_name != github.repository) }}
     runs-on: ubuntu-latest
-    container: quay.io/pypa/manylinux2014_x86_64
-    env:
-      # Disable output buffering in an attempt to get readable errors
-      PYTHONUNBUFFERED: '1'
     steps:
-      - name: Checkout
-        uses: actions/checkout@v3
+      - uses: actions/checkout@v5
         with:
           submodules: 'true'
-      
-      - name: Build
+
+      - name: Update pyproject.toml version
+        if: ${{ startsWith(github.ref, 'refs/tags/') }}
         shell: bash
         run: |
-          curl https://sh.rustup.rs -sSf | sh -s -- --default-toolchain stable -y && yum install -y openssl-devel
-          export PATH="$PATH:$HOME/.cargo/bin"
-          export PATH="/opt/python/cp38-cp38/bin:$PATH"
-          pip install -r requirements.txt
-          python setup.py bdist_wheel --py-limited-api=cp37 --plat-name manylinux2014_x86_64
-          auditwheel show dist/*.whl
-          pip install --force-reinstall dist/*.whl
-          python -c "import icicle"
-      
-      - name: Test
-        run: |
-          export PATH="/opt/python/cp38-cp38/bin:$PATH"
-          pip install -r tests/requirements.txt
-          python tests/example.py
-          python tests/invalid.py
-    
-      - name: Upload wheels
-        uses: actions/upload-artifact@v3
+          # Extract version from tag (strip 'v' prefix if present)
+          VERSION=${GITHUB_REF#refs/tags/}
+          VERSION=${VERSION#v}
+          echo "Extracted version: $VERSION"
+          
+          # Update version in pyproject.toml (works on both GNU and BSD sed)
+          sed -i.bak "s/^version = .*/version = \"$VERSION\"/" pyproject.toml
+          rm pyproject.toml.bak
+
+      - name: Build sdist
+        uses: PyO3/maturin-action@v1
         with:
-          name: wheels
+          command: sdist
+          args: --out dist
+
+      - name: Upload sdist
+        uses: actions/upload-artifact@v4
+        with:
+          name: wheels-sdist
           path: dist
 
   release:
     if: ${{ startsWith(github.ref, 'refs/tags/') }}
     runs-on: ubuntu-latest
-    needs: [windows, macos, linux]
+    needs: [linux, windows, macos, sdist]
     permissions:
       contents: write
       discussions: write
+      id-token: write
     steps:
       - name: Download wheels
-        uses: actions/download-artifact@v3
+        uses: actions/download-artifact@v5
         with:
-          name: wheels
+          pattern: wheels-*
+          merge-multiple: true
           path: dist
 
       - name: Publish to PyPI
-        uses: pypa/gh-action-pypi-publish@b7f401de30cb6434a1e19f805ff006643653240e # v1.8.10
+        uses: PyO3/maturin-action@v1
         with:
-          password: ${{ secrets.PYPI_API_TOKEN }}
-          packages-dir: dist/
+          command: upload
+          args: --non-interactive --skip-existing dist/*
 
       - name: Release
-        uses: softprops/action-gh-release@c9b46fe7aad9f02afd89b12450b780f52dacfb2d # master 2023-03-26
+        uses: softprops/action-gh-release@6da8fa9354ddfdc4aeace5fc48d7f679b5214090 # v2.4.1
         with:
           generate_release_notes: true
           files: dist/*

.python-version

@@ -0,0 +1 @@
+3.8

Cargo.toml

@@ -1,24 +1,26 @@
-# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
-
 [package]
 name = "icicle-python"
-version = "0.0.3"
 edition = "2021"
+rust-version = "1.90.0"
 
 [lib]
 name = "icicle"
-crate-type = ["cdylib"]
+crate-type = ["cdylib", "lib"]
+
+[[bin]]
+name = "tests"
+path = "tests.rs"
 
 [dependencies]
+pyo3 = { version = "0.27.1", features = ["indexmap", "abi3-py38"] }
 icicle-cpu = { path = "icicle-emu/icicle-cpu" }
 icicle-vm = { path = "icicle-emu/icicle-vm" }
 pcode = { path = "icicle-emu/sleigh/pcode" }
 sleigh-runtime = { path = "icicle-emu/sleigh/sleigh-runtime" }
-indexmap = "2.2.6"
-pyo3 = { version = "0.21.2", features = ["extension-module", "indexmap", "abi3-py37"] }
-target-lexicon = "0.12.7"
+indexmap = "*"
+target-lexicon = "*"
 tracing = "*"
-tracing-subscriber = "0.3.17"
+tracing-subscriber = "*"
 
 [build-dependencies]
-pyo3-build-config = "0.21.2"
+pyo3-build-config = "0.27.1"

README.md

@@ -1,32 +1,52 @@
 # icicle-python
 
-This project is an easy to use Python wrapper around [icicle-emu](https://github.com/icicle-emu/icicle-emu). You can read more about Icicle in the paper: [Icicle: A Re-designed Emulator for Grey-Box Firmware Fuzzing](https://arxiv.org/pdf/2301.13346.pdf).
+This project is an easy-to-use Python wrapper around [icicle-emu](https://github.com/icicle-emu/icicle-emu). You can read more about Icicle in the paper: [Icicle: A Re-designed Emulator for Grey-Box Firmware Fuzzing](https://arxiv.org/pdf/2301.13346.pdf).
 
 ## Installation
 
 You can install the [latest release](https://github.com/icicle-emu/icicle-python/releases) from [PyPI](https://pypi.org/project/icicle-emu):
 
 ```
-pip -m install icicle-emu
+pip install icicle-emu
 ```
 
 ## Development
 
-_Note_: You need to install [Rust 1.48](https://rustup.rs) or later to build from source.
+_Note_: You need to install [Rust 1.90](https://rustup.rs) or higher to build from source.
 
-Set up a virtual environment:
+### Install uv
 
 ```shell
-python -m venv venv
-# macOS/Linux
-source venv/bin/activate
-# Windows
-venv\Scripts\activate.bat
+# On Windows
+powershell -ExecutionPolicy ByPass -c "irm https://astral.sh/uv/install.ps1 | iex"
+# On macOS/Linux
+curl -LsSf https://astral.sh/uv/install.sh | sh
 ```
 
-Get the dependencies and build:
+### Build the project
 
 ```shell
-pip install -r requirements.txt
-python setup.py develop
+# Clone the repository with submodules
+git clone --recursive https://github.com/icicle-emu/icicle-python
+cd icicle-python
+
+# Install dependencies and build
+uv sync
+uv run maturin develop
+```
+
+### Running tests
+
+The `tests` folder contains tests that double as standalone examples. Prefix a function with `test_` to automatically run it:
+
+```shell
+uv run pytest -v
+```
+
+Alternatively you can `uv run tests/example.py` to run/debug the standalone example.
+
+### Building a wheel
+
+```shell
+uv build
 ```

build.rs

@@ -1,4 +1,4 @@
-// Reference: https://pyo3.rs/v0.18.3/building_and_distribution#macos
+// Reference: https://pyo3.rs/v0.27.1/building-and-distribution.html?highlight=build.rs#macos
 fn main() {
     pyo3_build_config::add_extension_module_link_args();
 }

exception_data_design.md

@@ -0,0 +1,201 @@
+# Exception Data Enhancement Design
+
+## Overview
+
+This document describes the design and implementation of enhanced exception information in icicle-python, which extends memory access exceptions to include the size of the access and the data being written.
+
+## Motivation
+
+Previously, when a memory access violation occurred during emulation, the exception only provided:
+- The type of violation (read/write/execute permission, unmapped memory, etc.)
+- The memory address where the violation occurred
+
+This limited information made debugging difficult because users couldn't determine:
+- How large the access was (1 byte? 8 bytes? 16 bytes?)
+- What data was being written (for write violations)
+
+These details are crucial for understanding what the emulated code was attempting to do when it failed.
+
+## Design Goals
+
+1. **Capture access size**: Record the number of bytes involved in the memory operation
+2. **Capture write data**: For write operations, preserve the actual bytes being written
+3. **Maintain simplicity**: Keep the API changes minimal and intuitive
+4. **Preserve performance**: Avoid overhead for the normal (non-exceptional) execution path
+
+## Implementation Strategy
+
+### Core Data Structure Changes
+
+The implementation required changes at multiple layers, from the core Rust emulator up through the Python bindings.
+
+#### 1. Exception Structure (Rust Core)
+
+**File**: `icicle-emu/icicle-cpu/src/cpu.rs`
+
+The `Exception` struct was extended with two new fields:
+```rust
+pub struct Exception {
+    pub code: u32,
+    pub value: u64,        // Already existed: the address
+    pub size: u32,         // NEW: size of the access
+    pub data: [u8; 16],    // NEW: up to 16 bytes of data
+}
+```
+
+Design decisions:
+- **Size as u32**: Memory accesses are typically 1-16 bytes, u32 provides plenty of range
+- **Data as [u8; 16]**: Fixed-size array avoids heap allocation while supporting common cases (up to 128-bit SIMD operations)
+- **Byte array over u64**: Preserves exact byte representation without endianness confusion
+
+#### 2. Memory Operation Handlers
+
+**File**: `icicle-emu/icicle-cpu/src/cpu.rs`
+
+The `UncheckedExecutor` implementation's memory operations were updated:
+
+```rust
+// For read operations - capture size only
+fn load_mem<const N: usize>(...) {
+    if let Err(err) = self.cpu.mem.read::<N>(...) {
+        self.cpu.exception = Exception::new_with_size(
+            ExceptionCode::from_load_error(err),
+            addr,
+            N as u32  // Capture the size
+        );
+    }
+}
+
+// For write operations - capture size and data
+fn store_mem<const N: usize>(..., value: [u8; N]) {
+    if let Err(err) = self.cpu.mem.write(...) {
+        self.cpu.exception = Exception::new_with_data(
+            ExceptionCode::from_store_error(err),
+            addr,
+            value  // Capture the actual bytes
+        );
+    }
+}
+```
+
+The generic const parameter `N` provides the size at compile time, which we capture in the exception.
+
+### Python Binding Layer
+
+#### 3. Python Bindings (Rust)
+
+**File**: `src/lib.rs`
+
+Added getters to expose the new fields to Python:
+```rust
+#[getter]
+pub fn get_exception_size(&self) -> u32 {
+    self.vm.cpu.exception.size
+}
+
+#[getter]
+pub fn get_exception_data(&self) -> Vec<u8> {
+    let size = self.vm.cpu.exception.size as usize;
+    if size == 0 {
+        Vec::new()
+    } else {
+        self.vm.cpu.exception.data[..size.min(16)].to_vec()
+    }
+}
+```
+
+The data getter returns only the valid bytes (up to size), not the entire 16-byte buffer.
+
+#### 4. Exception Propagation
+
+**File**: `src/lib.rs`
+
+Updated `raise_MemoryException` to include the new fields:
+```rust
+fn raise_MemoryException(message: String, e: MemError, size: u32, data: &[u8]) -> PyErr {
+    Python::with_gil(|py| {
+        let data_bytes = pyo3::types::PyBytes::new(py, data);
+        let args = (message, MemoryExceptionCode::from(e), size, data_bytes);
+        // ... create exception
+    })
+}
+```
+
+### Python Interface
+
+#### 5. Python Exception Class
+
+**File**: `python/icicle/__init__.py`
+
+Extended the `MemoryException` class:
+```python
+class MemoryException(Exception):
+    def __init__(self, message: str, code: MemoryExceptionCode,
+                 size: int = 0, data: bytes = b""):
+        super().__init__(message)
+        self.code = code
+        self.size = size
+        self.data = data
+```
+
+#### 6. Property Declarations
+
+Added properties to the `Icicle` class interface:
+```python
+@property
+def exception_size(self) -> int: ...
+
+@property
+def exception_data(self) -> bytes: ...
+```
+
+## Data Flow
+
+When a memory exception occurs:
+
+1. **CPU Execution**: The CPU attempts a memory operation through `load_mem` or `store_mem`
+2. **Exception Creation**: If the operation fails, an `Exception` struct is created with:
+   - The error code (type of violation)
+   - The address (already existed)
+   - The size (from the template parameter `N`)
+   - The data (for writes only)
+3. **Python Access**: Python code can access these fields via:
+   - `vm.exception_code` - the type of exception
+   - `vm.exception_value` - the address
+   - `vm.exception_size` - the size of access
+   - `vm.exception_data` - the bytes being written (empty for reads)
+
+## Use Cases
+
+This enhancement enables better debugging and analysis:
+
+1. **Security Analysis**: Understand buffer overflow attempts by seeing exactly what data was being written
+2. **Debugging**: Quickly identify whether a crash was from a byte, word, or larger access
+3. **Forensics**: Preserve the exact data that failed to write for later analysis
+4. **Testing**: Verify that code is attempting to write expected values
+
+## Example Usage
+
+```python
+from icicle import *
+
+vm = Icicle("x86_64")
+# ... setup and run code that causes exception ...
+
+if vm.exception_code == ExceptionCode.WritePerm:
+    print(f"Attempted to write {vm.exception_size} bytes to {hex(vm.exception_value)}")
+    print(f"Data: {vm.exception_data.hex()}")
+```
+
+## Performance Considerations
+
+- **Zero overhead for success path**: The new fields are only populated when an exception occurs
+- **Fixed-size storage**: Using `[u8; 16]` avoids heap allocation
+- **Const generics**: The size is known at compile time through Rust's const generics
+
+## Future Enhancements
+
+Potential improvements for future versions:
+- Support for larger data captures (>16 bytes) if needed for vector operations
+- Additional context like instruction pointer at time of exception
+- Register state snapshot at exception time

pyproject.toml

@@ -1,7 +1,41 @@
 [build-system]
-requires = [
-    "setuptools",
-    "wheel",
-    "setuptools-rust",
+requires = ["maturin>=1.7,<2.0"]
+build-backend = "maturin"
+
+[project]
+name = "icicle-emu"
+version = "1.0.0"
+description = "Python bindings for the Icicle emulator."
+readme = "README.md"
+license = {file = "LICENSE"}
+requires-python = ">=3.8"
+classifiers = [
+    "License :: OSI Approved :: Boost Software License 1.0 (BSL-1.0)",
+    "Intended Audience :: Developers",
+    "Programming Language :: Python :: 3",
+    "Development Status :: 5 - Production/Stable",
+    "Operating System :: POSIX",
+    "Operating System :: MacOS :: MacOS X",
+    "Operating System :: Microsoft :: Windows",
 ]
-build-backend = "setuptools.build_meta"
+
+[project.urls]
+Homepage = "https://github.com/icicle-emu/icicle-python"
+"Bug Tracker" = "https://github.com/icicle-emu/icicle-python/issues"
+
+[tool.maturin]
+python-source = "python"
+module-name = "icicle.icicle"
+features = ["pyo3/extension-module"]
+
+[dependency-groups]
+dev = [
+    "maturin>=1.7.8",
+    "pytest>=8.3.3",
+    "capstone>=5.0.6",
+    "keystone-engine>=0.9.2",
+]
+
+[tool.pytest.ini_options]
+testpaths = ["tests"]
+python_files = ["*.py"]

python/icicle/Ghidra/Processors/x86/data/languages/ia.sinc

@@ -1145,78 +1145,78 @@ macro ptr8(r,x) {
 
 macro push22(x) {
   mysave:2 = x;
-  SP = SP -2;
-  tmp:$(SIZE) = segment(SS,SP);
+  tmp:$(SIZE) = segment(SS,SP-2);
   *:2 tmp = mysave;
+  SP = SP-2;
 }
 
 macro push24(x) {
   mysave:4 = x;
-  SP = SP-4;
-  tmp:$(SIZE) = segment(SS,SP);
+  tmp:$(SIZE) = segment(SS,SP-4);
   *:4 tmp = mysave;
+  SP = SP-4;
 }
 
 macro push28(x) {
   mysave:8 = x;
-  SP = SP-8;
-  tmp:$(SIZE) = segment(SS,SP);
+  tmp:$(SIZE) = segment(SS,SP-8);
   *:8 tmp = mysave;
+  SP = SP-8;
 }
 
 macro push42(x) {
   mysave:2 = x;
-  $(STACKPTR) = $(STACKPTR) - 2;
-  *:2 $(STACKPTR) = mysave;
+  *:2 ($(STACKPTR)-2) = mysave;
+  $(STACKPTR) = $(STACKPTR)-2;
 }
 
 macro push44(x) {
   mysave:4 = x;
-  $(STACKPTR) = $(STACKPTR) - 4;
-  *:4 $(STACKPTR) = mysave;
+  *:4 ($(STACKPTR)-4) = mysave;
+  $(STACKPTR) = $(STACKPTR)-4;
 }
 
 macro pushseg44(x) {
   mysave:2 = x;
-  $(STACKPTR) = $(STACKPTR) - 4;
-  *:2 $(STACKPTR) = mysave;
+  *:2 ($(STACKPTR)-4) = mysave;
+  $(STACKPTR) = $(STACKPTR)-4;
 }
 
 macro push48(x) {
   mysave:8 = x;
-  $(STACKPTR) = $(STACKPTR) - 8;
-  *:8 $(STACKPTR) = mysave;
+  *:8 ($(STACKPTR)-8) = mysave;
+  $(STACKPTR) = $(STACKPTR)-8;
 }
 
 @ifdef IA64
 macro push82(x) {
   mysave:2 = x;
-  $(STACKPTR) = $(STACKPTR) - 2;
-  *:2 $(STACKPTR) = mysave;
+  *:2 ($(STACKPTR)-2) = mysave;
+  $(STACKPTR) = $(STACKPTR)-2;
 }
 
 macro push84(x) {
   mysave:4 = x;
-  $(STACKPTR) = $(STACKPTR) - 4;
-  *:4 $(STACKPTR) = mysave;
+  *:4 ($(STACKPTR)-4) = mysave;
+  $(STACKPTR) = $(STACKPTR)-4;
 }
 
 macro push88(x) {
   mysave:8 = x;
-  $(STACKPTR) = $(STACKPTR) - 8;
-  *:8 $(STACKPTR) = mysave;
+  *:8 ($(STACKPTR)-8) = mysave;
+  $(STACKPTR) = $(STACKPTR)-8;
 }
 
 macro pushseg82(x) {
   mysave:2 = x;
-  $(STACKPTR) = $(STACKPTR) - 2;
-  *:2 $(STACKPTR) = mysave;
+  *:2 ($(STACKPTR)-2) = mysave;
+  $(STACKPTR) = $(STACKPTR)-2;
 }
 
 macro pushseg88(x) {
   mysave:2 = x;
-  $(STACKPTR) = $(STACKPTR) - 8;
-  *:2 $(STACKPTR) = mysave;
+  *:2 ($(STACKPTR)-8) = mysave;
+  $(STACKPTR) = $(STACKPTR)-8;
 }
 @endif
 

python/icicle/__init__.py

@@ -1,12 +1,167 @@
-from .icicle import *
+from typing import List, Dict, Tuple
+from enum import Enum
+
+class MemoryProtection(Enum):
+    NoAccess = ...
+    ReadOnly = ...
+    ReadWrite = ...
+    ExecuteOnly = ...
+    ExecuteRead = ...
+    ExecuteReadWrite = ...
+
+class MemoryExceptionCode(Enum):
+    Unallocated = ...
+    Unmapped = ...
+    UnmappedRegisters = ...
+    Uninitialized = ...
+    ReadViolation = ...
+    WriteViolation = ...
+    ExecViolation = ...
+    ReadWatch = ...
+    WriteWatch = ...
+    Unaligned = ...
+    OutOfMemory = ...
+    SelfModifyingCode = ...
+    AddressOverflow = ...
+    Unknown = ...
+
+class RunStatus(Enum):
+    Running = ...
+    InstructionLimit = ...
+    Breakpoint = ...
+    Interrupted = ...
+    Halt = ...
+    Killed = ...
+    Deadlock = ...
+    OutOfMemory = ...
+    Unimplemented = ...
+    UnhandledException = ...
+
+class ExceptionCode(Enum):
+    NoException = ...
+    InstructionLimit = ...
+    Halt = ...
+    Sleep = ...
+    Syscall = ...
+    CpuStateChanged = ...
+    DivisionException = ...
+    ReadUnmapped = ...
+    ReadPerm = ...
+    ReadUnaligned = ...
+    ReadWatch = ...
+    ReadUninitialized = ...
+    WriteUnmapped = ...
+    WritePerm = ...
+    WriteWatch = ...
+    WriteUnaligned = ...
+    ExecViolation = ...
+    SelfModifyingCode = ...
+    OutOfMemory = ...
+    AddressOverflow = ...
+    InvalidInstruction = ...
+    UnknownInterrupt = ...
+    UnknownCpuID = ...
+    InvalidOpSize = ...
+    InvalidFloatSize = ...
+    CodeNotTranslated = ...
+    ShadowStackOverflow = ...
+    ShadowStackInvalid = ...
+    InvalidTarget = ...
+    UnimplementedOp = ...
+    ExternalAddr = ...
+    Environment = ...
+    JitError = ...
+    InternalError = ...
+    UnmappedRegister = ...
+    UnknownError = ...
+
+class Icicle:
+    def __init__(self, architecture: str, *,
+                 jit = True,
+                 jit_mem = True,
+                 shadow_stack = False,
+                 recompilation = True,
+                 track_uninitialized = False,
+                 optimize_instructions = True,
+                 optimize_block = False,
+                 tracing = False,
+                 ) -> None: ...
+
+    @property
+    def architecture(self) -> str: ...
+
+    @property
+    def exception_code(self) -> ExceptionCode: ...
+
+    @property
+    def exception_value(self) -> int: ...
+
+    @property
+    def exception_size(self) -> int: ...
+
+    @property
+    def exception_data(self) -> bytes: ...
+
+    icount: int
+
+    icount_limit: int
+
+    pc: int
+
+    sp: int
+
+    """
+    Physical memory capacity in pages (adjust when seeing OutOfMemory)
+    The default limit is set so that the maximum corresponds to ~400 MB of host memory.
+    """
+    mem_capacity: int
+
+    # TODO: API to get memory information?
+
+    def mem_map(self, address: int, size: int, protection: MemoryProtection): ...
+
+    def mem_unmap(self, address: int, size: int): ...
+
+    def mem_protect(self, address: int, size: int, protection: MemoryProtection): ...
+
+    def mem_read(self, address: int, size: int) -> bytes: ...
+
+    def mem_write(self, address: int, data: bytes) -> None: ...
+
+    def reg_list(self) -> Dict[str, Tuple[int, int]]: ...
+
+    def reg_offset(self, name: str) -> int: ...
+
+    def reg_size(self, name: str) -> int: ...
+
+    def reg_read(self, name: str) -> int: ...
+
+    def reg_write(self, name: str, value: int) -> None: ...
+
+    def reset(self): ...
+
+    def run(self) -> RunStatus: ...
+
+    def run_until(self, address: int) -> RunStatus: ...
+
+    def step(self, count: int) -> RunStatus: ...
+
+    def add_breakpoint(self, address: int) -> bool: ...
+
+    def remove_breakpoint(self, address: int) -> bool: ...
+
+def architectures() -> List[str]: ...
 
 class MemoryException(Exception):
-    def __init__(self, message: str, code: MemoryExceptionCode):
+    def __init__(self, message: str, code: MemoryExceptionCode, size: int = 0, data: bytes = b""):
         super().__init__(message)
         self.code = code
+        self.size = size
+        self.data = data
 
     def __str__(self):
-        return f"{super().__str__()}: {self.code}"
+        data_hex = self.data.hex() if self.data else "none"
+        return f"{super().__str__()}: {self.code} (size={self.size}, data={data_hex})"
 
 def __ghidra_init():
     import os
@@ -19,3 +174,6 @@ def __ghidra_init():
     raise FileNotFoundError("Ghidra processor definitions not found")
 
 __ghidra_init()
+
+# NOTE: This overrides the stubs at runtime with the actual implementation
+from .icicle import *

python/icicle/icicle.pyi

@@ -1,134 +0,0 @@
-from typing import List, Dict, Tuple
-from enum import Enum
-
-class MemoryProtection(Enum):
-    NoAccess = ...
-    ReadOnly = ...
-    ReadWrite = ...
-    ExecuteOnly = ...
-    ExecuteRead = ...
-    ExecuteReadWrite = ...
-
-class MemoryExceptionCode(Enum):
-    Unallocated = ...
-    Unmapped = ...
-    UnmappedRegisters = ...
-    Uninitialized = ...
-    ReadViolation = ...
-    WriteViolation = ...
-    ExecViolation = ...
-    ReadWatch = ...
-    WriteWatch = ...
-    Unaligned = ...
-    OutOfMemory = ...
-    SelfModifyingCode = ...
-    AddressOverflow = ...
-    Unknown = ...
-
-class RunStatus(Enum):
-    Running = ...
-    InstructionLimit = ...
-    Breakpoint = ...
-    Interrupted = ...
-    Halt = ...
-    Killed = ...
-    Deadlock = ...
-    OutOfMemory = ...
-    Unimplemented = ...
-    UnhandledException = ...
-
-class ExceptionCode(Enum):
-    NoException = ...
-    InstructionLimit = ...
-    Halt = ...
-    Sleep = ...
-    Syscall = ...
-    CpuStateChanged = ...
-    DivisionException = ...
-    ReadUnmapped = ...
-    ReadPerm = ...
-    ReadUnaligned = ...
-    ReadWatch = ...
-    ReadUninitialized = ...
-    WriteUnmapped = ...
-    WritePerm = ...
-    WriteWatch = ...
-    WriteUnaligned = ...
-    ExecViolation = ...
-    SelfModifyingCode = ...
-    OutOfMemory = ...
-    AddressOverflow = ...
-    InvalidInstruction = ...
-    UnknownInterrupt = ...
-    UnknownCpuID = ...
-    InvalidOpSize = ...
-    InvalidFloatSize = ...
-    CodeNotTranslated = ...
-    ShadowStackOverflow = ...
-    ShadowStackInvalid = ...
-    InvalidTarget = ...
-    UnimplementedOp = ...
-    ExternalAddr = ...
-    Environment = ...
-    JitError = ...
-    InternalError = ...
-    UnmappedRegister = ...
-    UnknownError = ...
-
-class Icicle:
-    def __init__(self, architecture: str, *,
-                 jit = True,
-                 jit_mem = True,
-                 shadow_stack = True,
-                 recompilation = True,
-                 track_uninitialized = False,
-                 optimize_instructions = True,
-                 optimize_block = True,
-                 tracing = False,
-                 ) -> None: ...
-
-    @property
-    def exception_code(self) -> ExceptionCode: ...
-
-    @property
-    def exception_value(self) -> int: ...
-
-    icount: int
-
-    icount_limit: int
-
-    # TODO: API to get memory information?
-
-    def mem_map(self, address: int, size: int, protection: MemoryProtection): ...
-
-    def mem_unmap(self, address: int, size: int): ...
-
-    def mem_protect(self, address: int, size: int, protection: MemoryProtection): ...
-
-    def mem_read(self, address: int, size: int) -> bytes: ...
-
-    def mem_write(self, address: int, data: bytes) -> None: ...
-
-    def reg_list(self) -> Dict[str, Tuple[int, int]]: ...
-
-    def reg_offset(self, name: str) -> int: ...
-
-    def reg_size(self, name: str) -> int: ...
-
-    def reg_read(self, name: str) -> int: ...
-
-    def reg_write(self, name: str, value: int) -> None: ...
-
-    def reset(self): ...
-
-    def run(self) -> RunStatus: ...
-
-    def run_until(self, address: int) -> RunStatus: ...
-
-    def step(self, count: int) -> RunStatus: ...
-
-    def add_breakpoint(self, address: int) -> bool: ...
-
-    def remove_breakpoint(self, address: int) -> bool: ...
-
-def architectures() -> List[str]: ...

requirements.txt

@@ -1,3 +0,0 @@
-setuptools
-wheel
-setuptools-rust

setup.cfg

@@ -1,34 +0,0 @@
-[metadata]
-name = icicle-emu
-version = 1.0.0
-url = https://github.com/icicle-emu/icicle-python
-project_urls =
-    Bug Tracker = https://github.com/icicle-emu/icicle-python/issues
-description = Python bindings for the Icicle emulator.
-long_description = file: README.md
-long_description_content_type = text/markdown
-classifiers =
-    License :: OSI Approved :: Boost Software License 1.0 (BSL-1.0)
-    Intended Audience :: Developers
-    Programming Language :: Python :: 3
-    Programming Language :: Python :: 3.7
-    Programming Language :: Python :: 3.8
-    Programming Language :: Python :: 3.9
-    Programming Language :: Python :: 3.10
-    Programming Language :: Python :: 3.11
-    Development Status :: 5 - Production/Stable
-    Operating System :: POSIX
-    Operating System :: MacOS :: MacOS X
-    Operating System :: Microsoft :: Windows
-
-[options]
-packages = icicle
-package_dir =
-    = python
-zip_safe = False
-setup_requires = setuptools-rust >= 0.12.1;
-python_requires = >=3.7
-
-# Reference: https://stackoverflow.com/a/64789489/1806760
-[options.package_data]
-icicle = Ghidra/**/*

setup.py

@@ -1,31 +0,0 @@
-#!/usr/bin/env python
-
-import sys
-from os import getenv
-from shutil import which
-from setuptools import find_packages, setup
-from setuptools_rust import RustExtension
-
-if __name__ == "__main__":
-    if "sdist" not in sys.argv and which("cargo") is None:
-        raise FileNotFoundError(f"Rust not found, visit https://rustup.rs for installation instructions")
-
-    ref_name = getenv("GITHUB_REF_NAME")
-    if getenv("GITHUB_REF", "").startswith("refs/tags/") and ref_name:
-        from pkg_resources import parse_version
-        try:
-            parse_version(ref_name)
-            print(f"injecting version = {ref_name} into setup.cfg")
-            with open("setup.cfg", "r") as f:
-                lines = f.readlines()
-            with open("setup.cfg", "w") as f:
-                for line in lines:
-                    if line.startswith("version = "):
-                        line = f"version = {ref_name}\n"
-                    f.write(line)
-        except Exception:
-            pass
-
-    setup(
-        rust_extensions=[RustExtension("icicle.icicle")],
-    )

src/lib.rs

@@ -1,22 +1,36 @@
 use std::borrow::Cow;
 use std::collections::HashMap;
 use icicle_cpu::mem::{Mapping, MemError, perm};
-use icicle_cpu::{ExceptionCode, VmExit};
+use icicle_cpu::{Cpu, ExceptionCode, ValueSource, VmExit};
 use pyo3::prelude::*;
-use icicle_vm;
-use icicle_vm::linux::LinuxCpu;
 use pyo3::exceptions::*;
-use target_lexicon;
 use indexmap::IndexMap;
+use target_lexicon::Architecture;
 use sleigh_runtime::NamedRegister;
 
 // References:
 // - https://pyo3.rs/main/conversions/tables
 // - https://pyo3.rs/main/class
 
-#[pyclass(module = "icicle")]
-#[derive(Clone)]
-enum MemoryProtection {
+struct X86FlagsRegHandler {
+    pub eflags: pcode::VarNode,
+}
+
+impl icicle_cpu::RegHandler for X86FlagsRegHandler {
+    fn read(&mut self, cpu: &mut Cpu) {
+        let eflags = icicle_vm::x86::eflags(cpu);
+        cpu.write_var::<u32>(self.eflags, eflags);
+    }
+
+    fn write(&mut self, cpu: &mut Cpu) {
+        let eflags = cpu.read_var::<u32>(self.eflags);
+        icicle_vm::x86::set_eflags(cpu, eflags);
+    }
+}
+
+#[pyclass(eq, eq_int, module = "icicle")]
+#[derive(Clone, Debug, PartialEq)]
+pub enum MemoryProtection {
     NoAccess,
     ReadOnly,
     ReadWrite,
@@ -25,9 +39,9 @@ enum MemoryProtection {
     ExecuteReadWrite,
 }
 
-#[pyclass(module = "icicle")]
-#[derive(Clone)]
-enum RunStatus {
+#[pyclass(eq, eq_int, module = "icicle")]
+#[derive(Clone, Debug, PartialEq)]
+pub enum RunStatus {
     /// The VM is still running.
     Running,
 
@@ -59,8 +73,9 @@ enum RunStatus {
     UnhandledException,
 }
 
-#[pyclass(module = "icicle")]
-enum MemoryExceptionCode {
+#[pyclass(eq, eq_int, module = "icicle")]
+#[derive(Clone, Debug, PartialEq)]
+pub enum MemoryExceptionCode {
     Unallocated,
     Unmapped,
     UnmappedRegister,
@@ -98,9 +113,9 @@ impl From<MemError> for MemoryExceptionCode {
     }
 }
 
-#[pyclass(module = "icicle", name = "ExceptionCode")]
-#[derive(Clone)]
-enum ExceptionCodePy {
+#[pyclass(eq, eq_int, module = "icicle", name = "ExceptionCode")]
+#[derive(Clone, Debug, PartialEq)]
+pub enum ExceptionCodePy {
     NoException = 0x0000,
 
     InstructionLimit = 0x0001,
@@ -198,7 +213,7 @@ impl From<ExceptionCode> for ExceptionCodePy {
 
 #[allow(non_snake_case)]
 fn raise_MemoryException(message: String, e: MemError) -> PyErr {
-    Python::with_gil(|py| {
+    Python::attach(|py| {
         let icicle = py.import("icicle").unwrap();
         let exception = icicle.getattr("MemoryException").unwrap();
         let args = (message, MemoryExceptionCode::from(e));
@@ -219,13 +234,14 @@ fn convert_protection(protection: MemoryProtection) -> u8 {
 }
 
 #[pyclass(unsendable, module = "icicle")]
-struct Icicle {
+pub struct Icicle {
+    architecture: String,
     vm: icicle_vm::Vm,
     regs: HashMap<String, NamedRegister>,
 }
 
 fn reg_find<'a>(i: &'a Icicle, name: &str) -> PyResult<&'a NamedRegister> {
-    let sleigh = i.vm.cpu.sleigh();
+    let sleigh = &i.vm.cpu.arch.sleigh;
     match sleigh.get_reg(name) {
         None => {
             i.regs.get(name.to_lowercase().as_str())
@@ -237,51 +253,143 @@ fn reg_find<'a>(i: &'a Icicle, name: &str) -> PyResult<&'a NamedRegister> {
     }
 }
 
+fn reg_var<'a>(i: &'a Icicle, name: &str) -> PyResult<pcode::VarNode> {
+    let var = reg_find(i, name)?.get_var();
+    var.ok_or(PyKeyError::new_err(format!("Register var too large: {name}")))
+}
+
 #[pymethods]
 impl Icicle {
     #[getter]
-    fn get_icount_limit(&mut self) -> u64 {
+    pub fn get_icount_limit(&mut self) -> u64 {
         self.vm.icount_limit
     }
 
     #[setter]
-    fn set_icount_limit(&mut self, value: u64) {
+    pub fn set_icount_limit(&mut self, value: u64) {
         self.vm.icount_limit = value;
     }
 
     #[getter]
-    fn get_icount(&mut self) -> u64 {
-        return self.vm.cpu.icount;
+    pub fn get_icount(&mut self) -> u64 {
+        self.vm.cpu.icount
     }
 
     #[setter]
-    fn set_icount(&mut self, value: u64) {
+    pub fn set_icount(&mut self, value: u64) {
         self.vm.cpu.icount = value;
     }
 
     #[getter]
-    fn get_exception_code(&self) -> ExceptionCodePy {
+    pub fn get_exception_code(&self) -> ExceptionCodePy {
         ExceptionCode::from_u32(self.vm.cpu.exception.code).into()
     }
 
     #[getter]
-    fn get_exception_value(&self) -> u64 {
+    pub fn get_exception_value(&self) -> u64 {
         self.vm.cpu.exception.value
     }
 
+    #[getter]
+    pub fn get_exception_size(&self) -> u32 {
+        self.vm.cpu.exception.size
+    }
+
+    #[getter]
+    pub fn get_exception_data(&self) -> Vec<u8> {
+        // For read exceptions, there should be no data (the read failed)
+        // For write exceptions, return the data that was attempted to be written
+        let code = ExceptionCode::from_u32(self.vm.cpu.exception.code);
+
+        use std::io::Write;
+        let mut f = std::fs::OpenOptions::new()
+            .create(true)
+            .append(true)
+            .open("debug_exception.log").unwrap();
+        writeln!(f, "exception code raw={}, parsed={:?}", self.vm.cpu.exception.code, code).unwrap();
+        writeln!(f, "data.len()={}, size={}", self.vm.cpu.exception.data.len(), self.vm.cpu.exception.size).unwrap();
+
+        // Check if this is a read exception
+        match code {
+            ExceptionCode::ReadUnmapped |
+            ExceptionCode::ReadPerm |
+            ExceptionCode::ReadUnaligned |
+            ExceptionCode::ReadWatch |
+            ExceptionCode::ReadUninitialized => {
+                writeln!(f, "Returning empty for read exception").unwrap();
+                // Read exceptions have no data
+                Vec::new()
+            }
+            _ => {
+                writeln!(f, "Returning data for non-read exception").unwrap();
+                // For other exceptions (writes), return the actual data
+                let size = self.vm.cpu.exception.size as usize;
+                let data_len = self.vm.cpu.exception.data.len();
+                if data_len == 0 {
+                    Vec::new()
+                } else {
+                    self.vm.cpu.exception.data[..size.min(data_len)].to_vec()
+                }
+            }
+        }
+    }
+
+    #[getter]
+    pub fn get_architecture(&self) -> String {
+        self.architecture.to_string()
+    }
+
+    #[getter]
+    pub fn get_pc(&self) -> u64 {
+        self.vm.cpu.read_pc()
+    }
+
+    #[setter]
+    pub fn set_pc(&mut self, address: u64) {
+        self.vm.cpu.write_pc(address)
+    }
+
+    #[getter]
+    pub fn get_sp(&mut self) -> u64 {
+        self.vm.cpu.read_reg(self.vm.cpu.arch.reg_sp)
+    }
+
+    #[setter]
+    pub fn set_sp(&mut self, address: u64) {
+        self.vm.cpu.write_reg(self.vm.cpu.arch.reg_sp, address)
+    }
+
+    #[getter]
+    pub fn get_mem_capacity(&self) -> usize {
+        self.vm.cpu.mem.capacity()
+    }
+
+    #[setter]
+    pub fn set_mem_capacity(&mut self, capacity: usize) -> PyResult<()> {
+        if self.vm.cpu.mem.set_capacity(capacity) {
+            return Ok(());
+        }
+        Err(
+            raise_MemoryException(
+                format!("Reducing memory capacity is not supported"),
+                MemError::Unknown,
+            )
+        )
+    }
+
     #[new]
     #[pyo3(signature = (
         architecture,
         jit = true,
         jit_mem = true,
-        shadow_stack = true,
+        shadow_stack = false,
         recompilation = true,
         track_uninitialized = false,
         optimize_instructions = true,
-        optimize_block = true,
+        optimize_block = false,
         tracing = false,
     ))]
-    fn new(
+    pub fn new(
         architecture: String,
         jit: bool,
         jit_mem: bool,
@@ -308,11 +416,11 @@ impl Icicle {
             }
         }
 
-        // Setup the CPU state for the target triple
+        // Set up the CPU state for the target triple
         let mut config = icicle_vm::cpu::Config::from_target_triple(
             format!("{architecture}-none").as_str()
         );
-        if config.triple.architecture == target_lexicon::Architecture::Unknown {
+        if config.triple.architecture == Architecture::Unknown {
             return Err(
                 PyException::new_err(format!("Unknown architecture: {architecture}"))
             );
@@ -327,38 +435,50 @@ impl Icicle {
         config.optimize_instructions = optimize_instructions;
         config.optimize_block = optimize_block;
 
-        let vm = icicle_vm::build(&config)
+        let mut vm = icicle_vm::build(&config)
             .map_err(|e| {
                 PyException::new_err(format!("VM build error: {e}"))
             })?;
 
         // Populate the lowercase register map
         let mut regs = HashMap::new();
-        let sleigh = vm.cpu.sleigh();
+        let sleigh = &vm.cpu.arch.sleigh;
         for reg in &sleigh.named_registers {
             let name = sleigh.get_str(reg.name);
             regs.insert(name.to_lowercase(), reg.clone());
         }
 
+        // Special handling for x86 flags
+        match config.triple.architecture {
+            Architecture::X86_32(_) | Architecture::X86_64 | Architecture::X86_64h => {
+                let eflags = sleigh.get_reg("eflags").unwrap().get_var().unwrap();
+                let reg_handler = X86FlagsRegHandler { eflags };
+                vm.cpu.add_reg_handler(eflags.id, Box::new(reg_handler));
+            }
+            _ => {}
+        }
+
         Ok(Icicle {
+            architecture,
             vm,
             regs,
         })
     }
 
-    fn __str__(&mut self) -> String {
+    pub fn __str__(&mut self) -> String {
         let arch = &self.vm.cpu.arch;
         let endianness = if arch.sleigh.big_endian {
             "big endian"
         } else {
             "little endian"
         };
-        format!("Icicle VM for {0:?} ({endianness})", arch.triple.architecture)
+        format!("Icicle VM for {0:?} ({endianness})", self.architecture)
     }
 
-    fn mem_map(&mut self, address: u64, size: u64, protection: MemoryProtection) -> PyResult<()> {
+    pub fn mem_map(&mut self, address: u64, size: u64, protection: MemoryProtection) -> PyResult<()> {
+        let init_perm = if self.vm.cpu.mem.track_uninitialized { perm::NONE } else { perm::INIT };
         let mapping = Mapping {
-            perm: convert_protection(protection),
+            perm: convert_protection(protection) | init_perm,
             value: 0,
         };
         if self.vm.cpu.mem.map_memory_len(address, size, mapping) {
@@ -373,7 +493,7 @@ impl Icicle {
         }
     }
 
-    fn mem_unmap(&mut self, address: u64, size: u64) -> PyResult<()> {
+    pub fn mem_unmap(&mut self, address: u64, size: u64) -> PyResult<()> {
         if self.vm.cpu.mem.unmap_memory_len(address, size) {
             Ok(())
         } else {
@@ -386,7 +506,7 @@ impl Icicle {
         }
     }
 
-    fn mem_protect(&mut self, address: u64, size: usize, protection: MemoryProtection) -> PyResult<()> {
+    pub fn mem_protect(&mut self, address: u64, size: usize, protection: MemoryProtection) -> PyResult<()> {
         self.vm.cpu.mem.update_perm(address, size as u64, convert_protection(protection))
             .map_err(|e| {
                 raise_MemoryException(
@@ -397,7 +517,7 @@ impl Icicle {
         Ok(())
     }
 
-    fn mem_read(&mut self, address: u64, size: usize) -> PyResult<Cow<[u8]>> {
+    pub fn mem_read(&mut self, address: u64, size: usize) -> PyResult<Cow<'_, [u8]>> {
         // Allocate a buffer
         let mut buffer = Vec::with_capacity(size);
         buffer.resize(size, 0);
@@ -410,10 +530,10 @@ impl Icicle {
                     e,
                 )
             })?;
-        return Ok(Cow::Owned(buffer));
+        Ok(Cow::Owned(buffer))
     }
 
-    fn mem_write(&mut self, address: u64, data: Vec<u8>) -> PyResult<()> {
+    pub fn mem_write(&mut self, address: u64, data: Vec<u8>) -> PyResult<()> {
         let size = data.len();
         self.vm.cpu.mem.write_bytes(address, &data[..], perm::NONE)
             .map_err(|e| {
@@ -424,37 +544,46 @@ impl Icicle {
             })
     }
 
-    fn reg_list(&self) -> PyResult<IndexMap<String, (u32, u8)>> {
+    pub fn reg_list(&self) -> PyResult<IndexMap<String, (u32, u8)>> {
         let mut result = IndexMap::new();
-        let sleigh = self.vm.cpu.sleigh();
+        let sleigh = &self.vm.cpu.arch.sleigh;
         for reg in &sleigh.named_registers {
             let name = sleigh.get_str(reg.name);
-            result.insert(name.to_string(), (reg.offset, reg.var.size));
+            let var = reg.get_var();
+            if let Some(var) = var {
+                result.insert(name.to_string(), (reg.offset, var.size));
+            }
         }
-        return Ok(result);
+        Ok(result)
     }
 
-    fn reg_offset(&self, name: &str) -> PyResult<u32> {
+    pub fn reg_offset(&self, name: &str) -> PyResult<u32> {
         Ok(reg_find(self, name)?.offset)
     }
 
-    fn reg_size(&self, name: &str) -> PyResult<u8> {
-        Ok(reg_find(self, name)?.var.size)
+    pub fn reg_size(&self, name: &str) -> PyResult<u8> {
+        Ok(reg_var(self, name)?.size)
     }
 
-    fn reg_read(&mut self, name: &str) -> PyResult<u64> {
-        Ok(self.vm.cpu.read_reg(reg_find(self, name)?.var))
+    pub fn reg_read(&mut self, name: &str) -> PyResult<u64> {
+        Ok(self.vm.cpu.read_reg(reg_var(self, name)?))
     }
 
-    fn reg_write(&mut self, name: &str, value: u64) -> PyResult<()> {
-        Ok(self.vm.cpu.write_reg(reg_find(self, name)?.var, value))
+    pub fn reg_write(&mut self, name: &str, value: u64) -> PyResult<()> {
+        let var = reg_var(self, name)?;
+        if var == self.vm.cpu.arch.reg_pc {
+            self.vm.cpu.write_pc(value);
+        } else {
+            self.vm.cpu.write_reg(var, value);
+        }
+        Ok(())
     }
 
-    fn reset(&mut self) {
+    pub fn reset(&mut self) {
         self.vm.reset();
     }
 
-    fn run(&mut self) -> RunStatus {
+    pub fn run(&mut self) -> RunStatus {
         match self.vm.run() {
             VmExit::Running => RunStatus::Running,
             VmExit::InstructionLimit => RunStatus::InstructionLimit,
@@ -469,7 +598,7 @@ impl Icicle {
         }
     }
 
-    fn run_until(&mut self, address: u64) -> RunStatus {
+    pub fn run_until(&mut self, address: u64) -> RunStatus {
         let breakpoint_added = self.vm.add_breakpoint(address);
         let status = self.run();
         if breakpoint_added {
@@ -478,7 +607,7 @@ impl Icicle {
         status
     }
 
-    fn step(&mut self, count: u64) -> RunStatus {
+    pub fn step(&mut self, count: u64) -> RunStatus {
         let old_limit = self.vm.icount_limit;
         self.vm.icount_limit = self.vm.cpu.icount.saturating_add(count);
         let status = self.run();
@@ -486,17 +615,17 @@ impl Icicle {
         status
     }
 
-    fn add_breakpoint(&mut self, address: u64) -> bool {
+    pub fn add_breakpoint(&mut self, address: u64) -> bool {
         self.vm.add_breakpoint(address)
     }
 
-    fn remove_breakpoint(&mut self, address: u64) -> bool {
+    pub fn remove_breakpoint(&mut self, address: u64) -> bool {
         self.vm.remove_breakpoint(address)
     }
 }
 
 #[pyfunction]
-fn architectures() -> PyResult<Vec<&'static str>> {
+pub fn architectures() -> PyResult<Vec<&'static str>> {
     Ok(vec![
         "i686",
         "x86_64",
@@ -508,7 +637,7 @@ fn architectures() -> PyResult<Vec<&'static str>> {
 /// the `lib.name` setting in the `Cargo.toml`, else Python will not be able to
 /// import the module.
 #[pymodule]
-fn icicle(_: Python<'_>, m: &PyModule) -> PyResult<()> {
+fn icicle(m: &Bound<'_, PyModule>) -> PyResult<()> {
     m.add_function(wrap_pyfunction!(architectures, m)?)?;
     m.add_class::<Icicle>()?;
     m.add_class::<MemoryProtection>()?;

src/main.rs

@@ -1,379 +0,0 @@
-use std::borrow::Cow;
-use std::collections::HashMap;
-use icicle_cpu::mem::{Mapping, perm};
-use icicle_cpu::{VmExit};
-use icicle_vm;
-use icicle_vm::linux::LinuxCpu;
-use target_lexicon;
-use indexmap::IndexMap;
-use sleigh_runtime::NamedRegister;
-
-#[allow(dead_code)]
-#[derive(Clone)]
-enum MemoryProtection {
-    NoAccess,
-    ReadOnly,
-    ReadWrite,
-    ExecuteOnly,
-    ExecuteRead,
-    ExecuteReadWrite,
-}
-
-struct Icicle {
-    vm: icicle_vm::Vm,
-    regs: HashMap<String, NamedRegister>,
-}
-
-fn convert_protection(protection: MemoryProtection) -> u8 {
-    match protection {
-        MemoryProtection::NoAccess => perm::NONE,
-        MemoryProtection::ReadOnly => perm::READ,
-        MemoryProtection::ReadWrite => perm::READ | perm::WRITE,
-        MemoryProtection::ExecuteOnly => perm::EXEC,
-        MemoryProtection::ExecuteRead => perm::EXEC | perm::READ,
-        MemoryProtection::ExecuteReadWrite => perm::EXEC | perm::READ | perm::WRITE,
-    }
-}
-
-fn reg_find<'a>(i: &'a Icicle, name: &str) -> Result<&'a NamedRegister, String> {
-    let sleigh = i.vm.cpu.sleigh();
-    match sleigh.get_reg(name) {
-        None => {
-            i.regs.get(name.to_lowercase().as_str())
-                .ok_or(
-                    format!("Register not found: {name}")
-                )
-        }
-        Some(r) => Ok(r),
-    }
-}
-
-impl Icicle {
-    #[allow(dead_code)]
-    fn get_icount_limit(&mut self) -> u64 {
-        self.vm.icount_limit
-    }
-
-    #[allow(dead_code)]
-    fn set_icount_limit(&mut self, value: u64) {
-        self.vm.icount_limit = value;
-    }
-
-    #[allow(dead_code)]
-    fn get_icount(&mut self) -> u64 {
-        return self.vm.cpu.icount;
-    }
-
-    #[allow(dead_code)]
-    fn set_icount(&mut self, value: u64) {
-        self.vm.cpu.icount = value;
-    }
-
-    fn new(
-        architecture: String,
-        jit: bool,
-        jit_mem: bool,
-        shadow_stack: bool,
-        recompilation: bool,
-        track_uninitialized: bool,
-        optimize_instructions: bool,
-        optimize_block: bool,
-        tracing: bool,
-    ) -> Result<Self, String> {
-        // Prevent mixing '_' and '-'
-        if architecture.split("-").count() != 1 {
-            return Err(
-                format!("Bad architecture format: {architecture}")
-            );
-        }
-
-        // TODO: support instantiating this multiple times
-        if tracing {
-            tracing_subscriber::fmt()
-                .with_max_level(tracing::Level::DEBUG)
-                .with_target(false)
-                .init();
-        }
-
-        // Setup the CPU state for the target triple
-        let mut config = icicle_vm::cpu::Config::from_target_triple(
-            format!("{architecture}-none").as_str()
-        );
-        if config.triple.architecture == target_lexicon::Architecture::Unknown {
-            return Err(
-                format!("Unknown architecture: {architecture}")
-            );
-        }
-
-        // Configuration
-        config.enable_jit = jit;
-        config.enable_jit_mem = jit_mem;
-        config.enable_shadow_stack = shadow_stack;
-        config.enable_recompilation = recompilation;
-        config.track_uninitialized = track_uninitialized;
-        config.optimize_instructions = optimize_instructions;
-        config.optimize_block = optimize_block;
-
-        let vm = icicle_vm::build(&config)
-            .map_err(|e| {
-                format!("VM build error: {e}")
-            })?;
-
-        // Populate the lowercase register map
-        let mut regs = HashMap::new();
-        let sleigh = vm.cpu.sleigh();
-        for reg in &sleigh.named_registers {
-            let name = sleigh.get_str(reg.name);
-            regs.insert(name.to_lowercase(), reg.clone());
-        }
-
-        Ok(Icicle {
-            vm,
-            regs,
-        })
-    }
-
-    fn __str__(&mut self) -> String {
-        let arch = &self.vm.cpu.arch;
-        let endianness = if arch.sleigh.big_endian {
-            "big endian"
-        } else {
-            "little endian"
-        };
-        format!("Icicle VM for {0:?} ({endianness})", arch.triple.architecture)
-    }
-
-    fn mem_map(&mut self, address: u64, size: u64, protection: MemoryProtection) -> Result<(), String> {
-        let mapping = Mapping {
-            perm: convert_protection(protection),
-            value: 0,
-        };
-        if self.vm.cpu.mem.map_memory_len(address, size, mapping) {
-            Ok(())
-        } else {
-            Err(
-                format!("Failed to map memory {address:X}[{size:X}]")
-            )
-        }
-    }
-
-    #[allow(dead_code)]
-    fn mem_unmap(&mut self, address: u64, size: u64) -> Result<(), String> {
-        if self.vm.cpu.mem.unmap_memory_len(address, size) {
-            Ok(())
-        } else {
-            Err(
-                format!("Failed to unmap memory {address:X}[{size:X}]")
-            )
-        }
-    }
-
-    fn mem_protect(&mut self, address: u64, size: usize, protection: MemoryProtection) -> Result<(), String> {
-        self.vm.cpu.mem.update_perm(address, size as u64, convert_protection(protection))
-            .map_err(|_| {
-                format!("Failed to protect memory {address:X}[{size:X}]")
-            })?;
-        Ok(())
-    }
-
-    #[allow(dead_code)]
-    fn mem_read(&mut self, address: u64, size: usize) -> Result<Cow<[u8]>, String> {
-        // Allocate a buffer
-        let mut buffer = Vec::with_capacity(size);
-        buffer.resize(size, 0);
-
-        // Read the memory
-        match self.vm.cpu.mem.read_bytes(address, &mut buffer[..], perm::NONE) {
-            Ok(_) => Ok(Cow::Owned(buffer)),
-            Err(_) => Err(format!("Failed to read memory {address:X}[{size:X}]"))
-        }
-    }
-
-    fn mem_write(&mut self, address: u64, data: Vec<u8>) -> Result<(), String> {
-        let size = data.len();
-        match self.vm.cpu.mem.write_bytes(address, &data[..], perm::NONE) {
-            Ok(_) => Ok(()),
-            Err(_) => Err(format!("Failed to write memory {address:X}[{size:X}]"))
-        }
-    }
-
-    #[allow(dead_code)]
-    fn reg_list(&self) -> IndexMap<String, (u32, u8)> {
-        let mut result = IndexMap::new();
-        let sleigh = self.vm.cpu.sleigh();
-        for reg in &sleigh.named_registers {
-            let name = sleigh.get_str(reg.name);
-            result.insert(name.to_string(), (reg.offset, reg.var.size));
-        }
-        return result;
-    }
-
-    #[allow(dead_code)]
-    fn reg_offset(&self, name: &str) -> Result<u32, String> {
-        Ok(reg_find(self, name)?.offset)
-    }
-
-    #[allow(dead_code)]
-    fn reg_size(&self, name: &str) -> Result<u8, String> {
-        Ok(reg_find(self, name)?.var.size)
-    }
-
-    fn reg_read(&mut self, name: &str) -> Result<u64, String> {
-        Ok(self.vm.cpu.read_reg(reg_find(self, name)?.var))
-    }
-
-    fn reg_write(&mut self, name: &str, value: u64) -> Result<(), String> {
-        Ok(self.vm.cpu.write_reg(reg_find(self, name)?.var, value))
-    }
-
-    #[allow(dead_code)]
-    fn reset(&mut self) {
-        self.vm.reset();
-    }
-
-    fn run(&mut self) -> VmExit {
-        self.vm.run()
-    }
-
-    #[allow(dead_code)]
-    fn run_until(&mut self, address: u64) -> VmExit {
-        let breakpoint_added = self.vm.add_breakpoint(address);
-        let status = self.run();
-        if breakpoint_added {
-            self.vm.remove_breakpoint(address);
-        }
-        status
-    }
-
-    #[allow(dead_code)]
-    fn step(&mut self, count: u64) -> VmExit {
-        let old_limit = self.vm.icount_limit;
-        self.vm.icount_limit = self.vm.cpu.icount.saturating_add(count);
-        let status = self.run();
-        self.vm.icount_limit = old_limit;
-        status
-    }
-
-    #[allow(dead_code)]
-    fn add_breakpoint(&mut self, address: u64) -> bool {
-        self.vm.add_breakpoint(address)
-    }
-
-    #[allow(dead_code)]
-    fn remove_breakpoint(&mut self, address: u64) -> bool {
-        self.vm.remove_breakpoint(address)
-    }
-}
-
-#[allow(dead_code)]
-fn architectures() -> Result<Vec<&'static str>, String> {
-    Ok(vec![
-        "i686",
-        "x86_64",
-        "aarch64",
-    ])
-}
-
-fn nx_start() {
-    let mut vm = Icicle::new(
-        "x86_64".to_string(),
-        false,
-        true,
-        true,
-        true,
-        false,
-        true,
-        true,
-        false,
-    ).unwrap();
-    let page = 0x10000;
-    vm.mem_map(page, 0x1000, MemoryProtection::ReadOnly).unwrap();
-    // <non-executable memory> inc eax; ret
-    vm.mem_write(page, b"\xFF\xC0\xC3".to_vec()).unwrap();
-    vm.reg_write("rip", page).unwrap();
-    let status = vm.run();
-    println!("status: {:?}", status);
-    println!("rip: {:#x}", vm.reg_read("rip").unwrap());
-}
-
-fn nx_middle() {
-    let mut vm = Icicle::new(
-        "x86_64".to_string(),
-        false,
-        true,
-        true,
-        true,
-        false,
-        true,
-        true,
-        false,
-    ).unwrap();
-    let page = 0x10000;
-    vm.mem_map(page, 0x2000, MemoryProtection::ExecuteRead).unwrap();
-    vm.mem_protect(page + 0x1000, 0x1000, MemoryProtection::ReadOnly).unwrap();
-    // inc eax; inc eax; <transition to non-executable region>; ret
-    let rip = page + 0x1000 - 2;
-    vm.mem_write(rip, b"\xFF\xC0\xFF\xC0\xC3".to_vec()).unwrap();
-    vm.reg_write("rip", rip).unwrap();
-    let status = vm.run();
-    println!("status: {:?}", status);
-    println!("rip: {:#x}", vm.reg_read("rip").unwrap());
-    println!("rax: {:#x}", vm.reg_read("rax").unwrap());
-}
-
-fn inv_start() {
-    let mut vm = Icicle::new(
-        "x86_64".to_string(),
-        false,
-        true,
-        true,
-        true,
-        false,
-        true,
-        true,
-        false,
-    ).unwrap();
-    let page = 0x10000;
-    vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead).unwrap();
-    // <invalid>; ret
-    vm.mem_write(page, b"\xFF\xFF\xC3".to_vec()).unwrap();
-    vm.reg_write("rip", page).unwrap();
-    let status = vm.run();
-    println!("status: {:?}", status);
-    println!("rip: {:#x}", vm.reg_read("rip").unwrap());
-    println!("rax: {:#x}", vm.reg_read("rax").unwrap());
-}
-
-fn inv_middle() {
-    let mut vm = Icicle::new(
-        "x86_64".to_string(),
-        false,
-        true,
-        true,
-        true,
-        false,
-        true,
-        true,
-        false,
-    ).unwrap();
-    let page = 0x10000;
-    vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead).unwrap();
-    // inc eax; <invalid>; ret
-    vm.mem_write(page, b"\xFF\xC0\xFF\xFF\xC3".to_vec()).unwrap();
-    vm.reg_write("rip", page).unwrap();
-    let status = vm.run();
-    println!("status: {:?}", status);
-    println!("rip: {:#x}", vm.reg_read("rip").unwrap());
-    println!("rax: {:#x}", vm.reg_read("rax").unwrap());
-}
-
-fn main() {
-    println!("=== NX (block start) ===");
-    nx_start();
-    println!("=== NX (block middle) ===");
-    nx_middle();
-    println!("=== Invalid instruction (block start) ===");
-    inv_start();
-    println!("=== Invalid instruction (block middle) ===");
-    inv_middle();
-}

tests.rs

@@ -0,0 +1,404 @@
+#![allow(unused)]
+
+use icicle::*;
+use pyo3::PyResult;
+use std::process::exit;
+
+// NOTE: https://github.com/rust-lang/rust-analyzer/issues/18752
+#[test]
+fn example() -> PyResult<()> {
+    Err(pyo3::exceptions::PyException::new_err("test"))
+}
+
+fn new_i686() -> PyResult<()> {
+    let mut vm = Icicle::new("i686".to_string(), true, true, false, true, false, true, false, false)?;
+    assert_eq!(vm.get_architecture(), "i686");
+    Ok(())
+}
+
+fn new_vm(jit: bool) -> PyResult<Icicle> {
+    Icicle::new(
+        "x86_64".to_string(),
+        jit,
+        true,
+        false,
+        true,
+        false,
+        true,
+        false,
+        false,
+    )
+}
+
+fn new_trace_vm(jit: bool) -> PyResult<Icicle> {
+    Icicle::new(
+        "x86_64".to_string(),
+        jit,
+        true,
+        false,
+        true,
+        false,
+        true,
+        false,
+        true,
+    )
+}
+
+fn nx_start() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+    let page = 0x10000;
+    vm.mem_map(page, 0x1000, MemoryProtection::ReadOnly)?;
+    // <non-executable memory> inc eax; ret
+    vm.mem_write(page, b"\xFF\xC0\xC3".to_vec())?;
+    vm.reg_write("rip", page)?;
+    let status = vm.run();
+    println!("status: {:?}", status);
+    println!("rip: {:#x}", vm.reg_read("rip")?);
+
+    Ok(())
+}
+
+fn nx_middle() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+    let page = 0x10000;
+    vm.mem_map(page, 0x2000, MemoryProtection::ExecuteRead)?;
+    vm.mem_protect(page + 0x1000, 0x1000, MemoryProtection::ReadOnly)?;
+    // inc eax; inc eax; <transition to non-executable region>; ret
+    let rip = page + 0x1000 - 2;
+    vm.mem_write(rip, b"\xFF\xC0\xFF\xC0\xC3".to_vec())?;
+    vm.reg_write("rip", rip)?;
+    let status = vm.run();
+    println!("status: {:?}", status);
+    println!("rip: {:#x}", vm.reg_read("rip")?);
+    println!("rax: {:#x}", vm.reg_read("rax")?);
+
+    Ok(())
+}
+
+fn inv_start() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+    let page = 0x10000;
+    vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead)?;
+    // <invalid>; ret
+    vm.mem_write(page, b"\xFF\xFF\xC3".to_vec())?;
+    vm.reg_write("rip", page)?;
+    let status = vm.run();
+    println!("status: {:?}", status);
+    println!("rip: {:#x}", vm.reg_read("rip")?);
+    println!("rax: {:#x}", vm.reg_read("rax")?);
+
+    Ok(())
+}
+
+fn inv_middle() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+    let page = 0x10000;
+    vm.mem_map(page, 0x1000, MemoryProtection::ExecuteRead)?;
+    // inc eax; <invalid>; ret
+    vm.mem_write(page, b"\xFF\xC0\xFF\xFF\xC3".to_vec())?;
+    vm.reg_write("rip", page)?;
+    let status = vm.run();
+    println!("status: {:?}", status);
+    println!("rip: {:#x}", vm.reg_read("rip")?);
+    println!("rax: {:#x}", vm.reg_read("rax")?);
+
+    Ok(())
+}
+
+fn block_optimization() -> PyResult<()> {
+    let mut vm: Icicle = Icicle::new(
+        "x86_64".to_string(),
+        true,
+        true,
+        true,
+        true,
+        false,
+        true,
+        true,
+        false,
+    )?;
+
+    // Memory setup
+    let addr: u64 = 0x140001A73;
+    let heap: u64 = 0x71000;
+    vm.mem_map(heap, 0x1000, MemoryProtection::ReadWrite)?;
+    vm.mem_write(heap + 4, b"\x37\x13\x00\x00".to_vec())?;
+    vm.mem_map(addr & !0xFFF, 0x1000, MemoryProtection::ExecuteRead)?;
+    vm.mem_write(addr, b"\x41\xc1\xea\x07\x41\x83\xe2\x1f\x74\x08\x44\x89\xd0\x48\x89\x54\xc6\x08\x49\x83\xc1\x04\x4c\x89\x0e\x4c\x89\xc9\x44\x8b\x11\x44\x89\xd0\xf7\xd0\x49\x89\xc9\xa8\x03\x0f\x84\x88\xf6\xff\xff\xeb\x4c\xcc".to_vec())?;
+
+    // Register setup
+    vm.reg_write("r9", heap)?;
+    vm.reg_write("r10", 0x13)?;
+    vm.reg_write("rip", addr)?;
+    vm.reg_write("rsi", heap + 0x100)?;
+
+    // Step through instructions
+    for i in 0..11 {
+        let rip = vm.reg_read("rip")?;
+        let rcx = vm.reg_read("rcx")?;
+        let r9 = vm.reg_read("r9")?;
+
+        println!("[{}] RIP: {:#x}, RCX: {:#x}, R9: {:#x}", i, rip, rcx, r9);
+
+        if rip == 0x140001A8F {
+            vm.reg_write("r9", 0x13370900)?;
+        }
+
+        vm.step(1);
+
+        if rip == 0x140001A9A {
+            if rcx != r9 {
+                println!("[BUG] expected rcx({:#x}) == r9({:#x})", rcx, r9);
+            } else {
+                println!("Everything works!");
+            }
+        }
+    }
+
+    Ok(())
+}
+
+fn rewind() -> PyResult<()> {
+    let mut vm = new_vm(true)?;
+
+    vm.mem_map(0x100, 0x20, MemoryProtection::ExecuteRead)?;
+    vm.mem_map(0x200, 0x20, MemoryProtection::ReadOnly)?;
+
+    vm.mem_write(0x100, b"\x55\xCC".to_vec())?; // push rbp
+    vm.reg_write("rbp", 0xF00)?;
+    vm.reg_write("rsp", 0x210)?;
+    vm.reg_write("rip", 0x100)?;
+    let status = vm.step(1);
+    println!("run status      : {:?}", status);
+    println!("exception code  : {:?}", vm.get_exception_code());
+    println!("exception value : {:#x}", vm.get_exception_value());
+    println!("stack pointer   : {:#x}", vm.reg_read("rsp")?);
+
+    Ok(())
+}
+
+fn execute_uninitialized() -> PyResult<()> {
+    let mut vm = Icicle::new(
+        "x86_64".to_string(),
+        true,
+        true,
+        false,
+        true,
+        true, // NOTE: setting this to true is not properly supported
+        true,
+        false,
+        false,
+    )?;
+
+    // \x48\x8d\x05\x01\x00\x00\x00\x90\x8a\x18\x90
+
+    vm.mem_map(0x100, 0x20, MemoryProtection::ExecuteOnly)?;
+    vm.mem_write(0x100, b"\x90\xFF\xC0".to_vec())?; // inc eax
+    vm.reg_write("rip", 0x100)?;
+    {
+        println!("[pre1] icount: {}", vm.get_icount());
+        let status = vm.step(2);
+        // NOTE: the real reason is that INIT is not set
+        println!("run status      : {:?}", status);
+        println!("exception code  : {:?}", vm.get_exception_code());
+        println!("exception value : {:#x}", vm.get_exception_value());
+        println!("rax             : {:#x}", vm.reg_read("rax")?);
+    }
+
+    {
+        println!("[pre2] icount: {}", vm.get_icount());
+        let status = vm.step(1);
+        // NOTE: the real reason is that INIT is not set
+        println!("run status      : {:?}", status);
+        println!("exception code  : {:?}", vm.get_exception_code());
+        println!("exception value : {:#x}", vm.get_exception_value());
+        println!("rax             : {:#x}", vm.reg_read("rax")?);
+        println!("[post] icount: {}", vm.get_icount());
+    }
+
+    // TODO: status is now UnhandledException, should be InstructionLimit
+    // on the next stpe it should be UnhandledException -> ExecViolation
+
+    Ok(())
+}
+
+fn execute_only() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+
+    vm.mem_map(0x100, 0x20, MemoryProtection::ExecuteOnly)?;
+    /*
+    0x100: lea rax, [rip]
+    0x107: nop
+    0x108: mov bl, byte ptr [rax]
+    0x10A: int3
+    */
+    vm.mem_write(
+        0x100,
+        b"\x48\x8d\x05\x00\x00\x00\x00\x90\x8a\x18\xCC".to_vec(),
+    )?; // nop
+    vm.reg_write("rip", 0x100)?;
+    vm.step(2);
+    let status = vm.step(1);
+    // NOTE: the real reason is that INIT is not set
+    println!("run status      : {:?}", status);
+    println!("exception code  : {:?}", vm.get_exception_code());
+    println!("exception value : {:#x}", vm.get_exception_value());
+    println!("bl: {:#x}", vm.reg_read("bl")?);
+    println!("rip: {:#x}", vm.reg_read("rip")?);
+
+    Ok(())
+}
+
+fn self_modifying() -> PyResult<()> {
+    // TODO: add a self-modifying code check (where the previously-executed code is written to)
+
+    Ok(())
+}
+
+fn step_modify_rip() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+    vm.mem_map(0x100, 0x20, MemoryProtection::ExecuteRead)?;
+
+    // 0x100:  48 01 d8                add    rax,rbx
+    // 0x103:  48 83 e9 05             sub    rcx,0x5
+    // 0x107:  48 89 d9                mov    rcx,rbx
+    // 0x10a:  90                      nop
+    // 0x10b:  90                      nop
+    vm.mem_write(
+        0x100,
+        b"\x48\x01\xD8\x48\x83\xE9\x05\x48\x89\xD9\x90\x90\xCC".to_vec(),
+    )?;
+
+    vm.reg_write("rax", 0xF00)?;
+    vm.reg_write("rbx", 0x210)?;
+    vm.reg_write("rip", 0x100)?;
+
+    println!("starting run at {:#x}", vm.reg_read("rip")?);
+    let mut status = vm.step(1);
+
+    println!(
+        "ending run at {:#x} (status: {:?})",
+        vm.reg_read("rip")?,
+        status
+    );
+    vm.reg_write("rip", 0x100)?;
+    //vm.write_pc(0x100);
+    //println!("pc: {:#x}", vm.read_pc());
+    println!("rip rewritten {:#x}", vm.reg_read("rip")?);
+    status = vm.step(1);
+    println!(
+        "ending run at {:#x} (status: {:?})",
+        vm.reg_read("rip")?,
+        status
+    );
+
+    Ok(())
+}
+
+fn eflags_reconstruction() -> PyResult<()> {
+    let mut vm = new_vm(false)?;
+    vm.mem_map(0x100, 0x20, MemoryProtection::ExecuteRead)?;
+
+    vm.mem_write(0x100, b"\x48\x01\xD8\xCC".to_vec())?;
+    vm.reg_write("rax", 0x7FFFFFFFFFFFFFFF)?;
+    vm.reg_write("rbx", 0x1)?;
+
+    let of_mask = (1 << 11) as u64;
+
+    {
+        let eflags = vm.reg_read("eflags")?;
+        let of = vm.reg_read("OF")?;
+        let of_set = (eflags & of_mask) == of_mask;
+        println!("[pre] eflags: {:#x}, OF: {:#x} == {}", eflags, of, of_set);
+    }
+
+    vm.set_pc(0x100);
+    let status = vm.step(1);
+    println!("run status: {:?}", status);
+
+    {
+        let eflags = vm.reg_read("eflags")?;
+        let rflags = vm.reg_read("rflags")?;
+        let of = vm.reg_read("OF")?;
+        let of_set = (eflags & of_mask) == of_mask;
+        println!(
+            "[post] eflags: {:#x} == {:#x}, OF: {:#x} == {}",
+            eflags, rflags, of, of_set
+        );
+    }
+
+    {
+        vm.reg_write("OF", 0)?;
+        let eflags = vm.reg_read("eflags")?;
+        let of = vm.reg_read("OF")?;
+        let of_set = (eflags >> 11) & 1;
+        println!("[OF=0] eflags: {:#x}, OF: {:#x} == {}", eflags, of, of_set);
+    }
+
+    {
+        let mut eflags = vm.reg_read("eflags")?;
+        eflags |= of_mask;
+        vm.reg_write("rflags", eflags)?;
+        let of = vm.reg_read("OF")?;
+        let of_set = (eflags >> 11) & 1;
+        println!(
+            "[rflags|={:#x}] eflags: {:#x}, OF: {:#x} == {}",
+            of_mask, eflags, of, of_set
+        );
+    }
+
+    Ok(())
+}
+
+fn main() {
+    // Make sure the GHIDRA_SRC environment variable is valid
+    match std::env::var("GHIDRA_SRC") {
+        Ok(ghidra_src) => {
+            // Make sure the directory $GHIDRA_SRC/Ghidra/Processors exists
+            if !std::path::Path::new(&ghidra_src)
+                .join("Ghidra")
+                .join("Processors")
+                .exists()
+            {
+                println!("GHIDRA_SRC environment variable invalid!");
+                exit(1);
+            }
+            println!("GHIDRA_SRC: {}", ghidra_src);
+        }
+        Err(_) => {
+            println!("GHIDRA_SRC environment variable not set!");
+            exit(1);
+        }
+    }
+
+    let tests: Vec<(&str, fn() -> PyResult<()>)> = vec![
+        ("New i686", new_i686),
+        ("NX (block start)", nx_start),
+        ("NX (block middle)", nx_middle),
+        ("Invalid instruction (block start)", inv_start),
+        ("Invalid instruction (block middle)", inv_middle),
+        ("Block optimization bug", block_optimization),
+        ("Rewind", rewind),
+        ("Execute only", execute_only),
+        ("Execute uninitialized", execute_uninitialized),
+        ("Step modify rip", step_modify_rip),
+        ("EFlags reconstruction", eflags_reconstruction),
+    ];
+
+    let mut success = 0;
+    for (name, f) in tests.iter() {
+        println!("=== {} ===", name);
+        match f() {
+            Ok(_) => {
+                success += 1;
+                println!("[OK]");
+            }
+            Err(e) => {
+                println!("[ERROR] {}", e);
+            }
+        }
+    }
+
+    println!("{}/{} tests passed", success, tests.len());
+    exit(if success == tests.len() { 0 } else { 1 });
+}

tests/blockopt.py

@@ -0,0 +1,70 @@
+try:
+    xfail = __import__("pytest").mark.xfail(reason="Known broken")
+except ImportError:
+    xfail = lambda func: func
+
+from icicle import *
+
+"""
+issue: https://github.com/icicle-emu/icicle-emu/issues/64
+
+mchesser:
+Yeah, an assumption that the block optimizer makes is that there will be no external modifications to registers within a blocks. This issue can be reproduced with something as simple as:
+
+[4c 89 c9] "MOV RCX, R9"
+[49 89 c9] "MOV R9, RCX"
+Which optimizes to the following Pcode:
+
+<L0> (entry=0x0):
+	instruction(0x0)
+	RCX = R9
+	instruction(0x3)
+Without this assumption, it is essentially impossible to perform any optimization that cross instruction boundaries.
+
+That said there are a couple of ways that this could be made better:
+
+Disable block-level optimizations by default (or remove them completely) -- in general they don't actually help that much for performance and after 802ab0c, most of the optimizations should already be done by Cranelift, which affects full-block execution anyway.
+Only apply optimizations to the JIT-blocks, meaning the interpreter (which is what is used for single stepping) executes the unoptimized pcode. The emulator checks some preconditions to ensure that the block will either be executed to completion (or to some known exit points) before entering the JIT.
+Warn when "reg_write" is performed inside of a block when block-level optimizations are enabled.
+Automatically de-optimize the block if a manual reg-write is performed in it.
+Bypass the code-cache and disable optimizations when performing single stepping.
+Add more control over the optimization process (e.g. const-prop flags, but not GPRs).
+I'm thinking that (1.) is probably the best solution the near term. Currently the main reason for the block-level optimizations is to simplify some static analysis that occurs later in my other work (fuzzing) and make the pcode more "readable".
+
+However, I want to potentially move towards (2.) in the future to allow for more aggressive optimizations in certain cases.
+"""
+@xfail
+def test_blockopt():
+    emu = Icicle("x86_64", jit=True, optimize_block=True, tracing=True)
+
+    instructions = bytes.fromhex("41 C1 EA 07 41 83 E2 1F 74 08 44 89 D0 48 89 54 C6 08 49 83 C1 04 4C 89 0E 4C 89 C9 44 8B 11 44 89 D0 F7 D0 49 89 C9 A8 03 0F 84 88 F6 FF FF EB 4C".replace(" ", ""))
+
+    addr = 0x140001A73
+    heap = 0x71000
+    emu.mem_map(heap, 0x1000, MemoryProtection.ReadWrite)
+    emu.mem_write(heap + 4, 0x1337.to_bytes(4, "little"))
+    emu.mem_map(addr & ~0xFFF, 0x1000, MemoryProtection.ExecuteRead)
+    emu.mem_write(addr, instructions)
+    emu.reg_write("r9", heap)
+    emu.reg_write("r10", 0x13)
+    emu.reg_write("rip", addr)
+    emu.reg_write("rsi", heap + 0x100)
+
+    for i in range(11):
+        rip = emu.reg_read("rip")
+        rcx = emu.reg_read("rcx")
+        r9 = emu.reg_read("r9")
+        print(f"[{i}] RIP: {hex(rip)}, RCX: {hex(rcx)}, R9: {hex(r9)}")
+
+        if rip == 0x140001A8F:
+            emu.reg_write("r9", 0x13370900)
+
+        emu.step(1)
+
+        if rip == 0x140001A9A:
+            assert rcx == r9, f"expected rcx({hex(rcx)}) == r9({hex(r9)})"
+
+    print("Everything works!")
+
+if __name__ == "__main__":
+    test_blockopt()

tests/conftest.py

@@ -0,0 +1,9 @@
+import sys
+import pytest
+
+def pytest_collection_modifyitems(config, items):
+    if sys.platform == "darwin":
+        skip_macos = pytest.mark.skip(reason="Skipped on macOS")
+        for item in items:
+            if "example.py" in str(item.fspath):
+                item.add_marker(skip_macos)

tests/example.py

@@ -1,8 +1,7 @@
 import icicle
-import keystone
-import capstone
 
 def assemble(code: str, addr: int = 0) -> bytes:
+    import keystone
     ks = keystone.Ks(keystone.KS_ARCH_X86, keystone.KS_MODE_64)
     encoding, count = ks.asm(code, addr)
     if encoding is None:
@@ -10,6 +9,7 @@ def assemble(code: str, addr: int = 0) -> bytes:
     return bytes(encoding)
 
 def disassemble(code: bytes, addr: int = 0, max_count = 1000) -> str:
+    import capstone
     result = ""
     cs = capstone.Cs(capstone.CS_ARCH_X86, capstone.CS_MODE_64)
     count = 0
@@ -30,7 +30,7 @@ def disassemble(code: bytes, addr: int = 0, max_count = 1000) -> str:
             addr += size
     return result
 
-def old_test():
+def test_old():
     buf = assemble("mov eax, ebx\nnop")
     print(disassemble(buf, 0))
     print(assemble("mov eax, ebx").hex())
@@ -60,9 +60,7 @@ def old_test():
     data = vm.mem_read(addr, 4)
     print(data, type(data))
 
-def main():
-    old_test()
-
+def test_new():
     print("")
     vm = icicle.Icicle("x86_64", jit=False)
     print(vm)
@@ -91,5 +89,9 @@ nop
         print(f"rax: {hex(vm.reg_read('rax'))}")
         assert False, "Should be unreachable"
 
+def main():
+    test_old()
+    test_new()
+
 if __name__ == "__main__":
     main()

tests/exception_data.py

@@ -0,0 +1,131 @@
+#!/usr/bin/env python3
+"""Test script to verify that exceptions now include size and data fields."""
+
+import sys
+sys.path.insert(0, './python')
+
+from icicle import *
+
+def test_write_exception():
+    """Test that write exceptions from CPU include size and data."""
+    print("Testing CPU write exception with size and data...")
+
+    # Create a VM
+    vm = Icicle("x86_64", jit=False)
+
+    # Map some executable memory for our code
+    code_page = 0x10000
+    vm.mem_map(code_page, 0x1000, MemoryProtection.ExecuteReadWrite)
+
+    # Map a read-only page that we'll try to write to
+    readonly_page = 0x20000
+    vm.mem_map(readonly_page, 0x1000, MemoryProtection.ReadOnly)
+
+    # Write some code that tries to write to read-only memory
+    # mov rax, 0x20000  (address of read-only page)
+    # mov rbx, 0x0102030405060708
+    # mov [rax], rbx
+    code = bytes.fromhex("48b80000020000000000" + "48bb0807060504030201" + "488918")
+    vm.mem_write(code_page, code)
+
+    # Execute the code
+    vm.reg_write("rip", code_page)
+
+    status = vm.run()
+    print(f"[OK] Execution stopped with status: {status}")
+    print(f"  - Exception code: {vm.exception_code}")
+    print(f"  - Exception value (address): 0x{vm.exception_value:x}")
+    print(f"  - Exception size: {vm.exception_size}")
+    print(f"  - Exception data: {vm.exception_data.hex() if vm.exception_data else 'none'}")
+
+    # The exception should be a write permission error
+    assert vm.exception_code == ExceptionCode.WritePerm
+    assert vm.exception_value == readonly_page
+    print("[OK] Write exception captured with size and data!")
+
+def test_read_exception():
+    """Test that read exceptions include size but no data."""
+    print("Testing CPU read exception with size...")
+
+    # Create a VM
+    vm = Icicle("x86_64", jit=False)
+
+    # Map some executable memory for our code
+    code_page = 0x10000
+    vm.mem_map(code_page, 0x1000, MemoryProtection.ExecuteReadWrite)
+
+    # Write some code that tries to read from unmapped memory
+    # mov rax, 0xDEADBEEF
+    # mov bx, word [rax]
+    code = bytes.fromhex("48B8EFBEADDE00000000" + "668B18")  # mov rax, 0xdeadbeef; mov bx, word [rax]
+    vm.mem_write(code_page, code)
+
+    # Execute the code
+    vm.reg_write("rip", code_page)
+
+    status = vm.run()
+    print(f"[OK] Execution stopped with status: {status}")
+    print(f"  - Exception code: {vm.exception_code}")
+    print(f"  - Exception value (address): 0x{vm.exception_value:x}")
+    print(f"  - Exception size: {vm.exception_size}")
+    print(f"  - Exception data: {vm.exception_data.hex() if vm.exception_data else '<empty>'}")
+
+    # The exception should be a read unmapped error
+    assert vm.exception_code == ExceptionCode.ReadUnmapped, vm.exception_code
+    assert vm.exception_value == 0xDEADBEEF
+    assert vm.exception_size == 2  # 16-bit read
+    # For read exceptions, data field should be empty (no actual data was read)
+    assert len(vm.exception_data) == 0, f"Read exceptions should have no data, but got: {vm.exception_data.hex()}"
+    print("[OK] Read exception captured with size but no data!")
+
+def test_execution_exception():
+    """Test execution exceptions from the CPU."""
+    print("\nTesting CPU execution exception with size...")
+
+    # Create a VM
+    vm = Icicle("x86_64", jit=False)
+
+    # Map memory as read-write (not executable)
+    page = 0x10000
+    vm.mem_map(page, 0x1000, MemoryProtection.ReadWrite)
+
+    # Write some code that tries to write to unmapped memory
+    # mov rax, 0xDEADBEEF
+    # mov [rax], rbx
+    code = bytes.fromhex("48b8efbeadde00000000488918")
+    vm.mem_write(page, code)
+
+    # Map the page as executable now
+    vm.mem_protect(page, 0x1000, MemoryProtection.ExecuteRead)
+
+    # Execute the code
+    vm.reg_write("rip", page)
+    vm.reg_write("rbx", 0x4142434445464748)  # Some test data
+
+    status = vm.run()
+    print(f"[OK] Execution stopped with status: {status}")
+    print(f"  - Exception code: {vm.exception_code}")
+    print(f"  - Exception value (address): 0x{vm.exception_value:x}")
+    print(f"  - Exception size: {vm.exception_size}")
+    print(f"  - Exception data: {vm.exception_data.hex() if vm.exception_data else 'none'}")
+
+    # The exception should be a write to unmapped memory
+    assert vm.exception_code == ExceptionCode.WriteUnmapped
+    assert vm.exception_value == 0xDEADBEEF
+    assert vm.exception_size == 8  # 64-bit write
+    # Check that we got the data that was trying to be written
+    expected_data = (0x4142434445464748).to_bytes(8, 'little')
+    assert vm.exception_data == expected_data, f"Data mismatch: {vm.exception_data.hex()} != {expected_data.hex()}"
+    print("[OK] CPU exception data matches!")
+
+def main():
+    print("=== Testing Extended Exception Information ===\n")
+
+    test_write_exception()
+    test_read_exception()
+    test_execution_exception()
+
+    print("\n=== All tests passed! ===")
+
+if __name__ == "__main__":
+    main()

tests/invalid.py

@@ -9,7 +9,7 @@ Scenarios:
 
 from icicle import *
 
-def nx():
+def test_nx():
     vm = Icicle("x86_64", jit=False)
     page = 0x10000
     vm.mem_map(page, 0x1000, MemoryProtection.ReadOnly)
@@ -22,7 +22,7 @@ def nx():
     assert vm.exception_code == ExceptionCode.ExecViolation
     assert vm.exception_value == page
 
-def inv_start():
+def test_inv_start():
     vm = Icicle("x86_64", jit=False)
     page = 0x10000
     vm.mem_map(page, 0x1000, MemoryProtection.ExecuteRead)
@@ -35,7 +35,7 @@ def inv_start():
     assert vm.exception_code == ExceptionCode.InvalidInstruction
     assert vm.exception_value == page
 
-def inv_middle():
+def test_inv_middle():
     vm = Icicle("x86_64", jit=False)
     page = 0x10000
     vm.mem_map(page, 0x1000, MemoryProtection.ExecuteRead)
@@ -50,11 +50,11 @@ def inv_middle():
 
 def main():
     print("=== NX ===")
-    nx()
+    test_nx()
     print("=== Invalid instruction (block start) ===")
-    inv_start()
+    test_inv_start()
     print("=== Invalid instruction (block middle) ===")
-    inv_middle()
+    test_inv_middle()
     print("\nSUCCESS")
 
 if __name__ == "__main__":

tests/issue32.py

@@ -0,0 +1,35 @@
+# https://github.com/icicle-emu/icicle-python/issues/32
+from icicle import Icicle, MemoryProtection, RunStatus, ExceptionCode
+
+def test_memhook():
+    data = bytes.fromhex(
+        "A1 FF FF 01 00"        # mov     eax, [0x1FFFF]
+        "B8 02 00 00 00"        # mov     eax, 2
+        "66 A3 A0 B3 01 10"     # mov     [0x1001B3A0], ax
+    )
+
+    ice = Icicle("i686")
+    ice.mem_map(0, 0x100, MemoryProtection.ExecuteOnly)
+    ice.mem_write(0, data)
+    status = ice.step(1)
+    assert status == RunStatus.UnhandledException
+    assert ice.exception_code == ExceptionCode.ReadUnmapped
+    assert ice.reg_read("eip") == 0
+
+    ice.mem_map(0x10000, 0x20000, MemoryProtection.ExecuteOnly)
+    status = ice.step(1)
+    assert status == RunStatus.UnhandledException
+    assert ice.exception_code == ExceptionCode.ReadPerm
+    assert ice.reg_read("eip") == 0
+
+    ice.mem_protect(0x1FFFF, 4, MemoryProtection.ExecuteReadWrite)
+    status = ice.step(1)
+    assert status == RunStatus.InstructionLimit
+
+    assert ice.reg_read("eip") == 5
+    assert ice.reg_read("eax") == 0
+
+    print("SUCCESS")
+
+if __name__ == "__main__":
+    test_memhook()

tests/requirements.txt

@@ -1,2 +0,0 @@
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-capstone==4.0.2

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